mirror of https://github.com/VLSIDA/OpenRAM.git
remove remaining cs_buf functions
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@ -453,12 +453,6 @@ class control_logic_delay(design.design):
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mod=self.clk_buf_driver)
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self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
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def create_cs_buf_row(self): # TODO: place and route
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""" Create the multistage and gated chip select buffer """
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self.cs_buf_inst = self.add_inst(name="csbuf",
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mod=self.clk_buf_driver)
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self.connect_inst(["cs", "cs_buf", "vdd", "gnd"])
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def place_clk_buf_row(self, row):
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x_offset = self.control_x_offset
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