use packages for imports in modules

compiler/modules/control_logic_delay.py

@@ -5,16 +5,16 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
+from base import design
 import debug
 from sram_factory import factory
 import math
-from vector import vector
+from base import vector
 from globals import OPTS
-import logical_effort
+from base import logical_effort
 
 
-class control_logic_delay(design.design):
+class control_logic_delay(design):
     """
     Dynamically generated Control logic for the total SRAM circuit.
     Variant: delay-based
@@ -44,7 +44,7 @@ class control_logic_delay(design.design):
         self.num_words = num_rows * words_per_row
 
         self.enable_delay_chain_resizing = False
-        self.inv_parasitic_delay = logical_effort.logical_effort.pinv
+        self.inv_parasitic_delay = logical_effort.pinv
 
         # Determines how much larger the sen delay should be. Accounts for possible error in model.
         # FIXME: This should be made a parameter

compiler/modules/multi_delay_chain.py

@@ -6,13 +6,13 @@
 # All rights reserved.
 #
 import debug
-import design
-from vector import vector
+from base import design
+from base import vector
 from globals import OPTS
 from sram_factory import factory
 
 
-class multi_delay_chain(design.design):
+class multi_delay_chain(design):
     """
     Generate a delay chain with the given number of stages, fanout, and output pins.
     Fanout list contains the electrical effort (fanout) of each stage.
@@ -34,7 +34,7 @@ class multi_delay_chain(design.design):
         # number of inverters including any fanout loads.
         self.fanout_list = fanout_list
         self.rows = len(self.fanout_list)
-        
+ 
         # defaults to signle output at end of delay chain
         if not pinout_list:
             self.pinout_list = [self.rows] # TODO: check for off-by-one here