mirror of https://github.com/VLSIDA/OpenRAM.git
routing mistake in route_wlen
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@ -563,7 +563,7 @@ class control_logic_delay(design.design):
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out_pin = self.wl_en_unbuf_and_inst.get_pin("Z")
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out_pos = out_pin.center()
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in_pin = self.p_en_bar_driver_inst.get_pin("A")
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in_pin = self.wl_en_driver_inst.get_pin("A")
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in_pos = in_pin.center()
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mid1 = vector(in_pos.x, out_pos.y)
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self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
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