add flatglob to tech file; sky130 replica col lvs working

This commit is contained in:
Jesse Cirimelli-Low 2022-08-22 15:30:11 -07:00
parent caba726cfe
commit 11fa0777e8
3 changed files with 35 additions and 10 deletions

View File

@ -26,7 +26,6 @@ import shutil
import debug
from globals import OPTS
from .run_script import *
# Keep track of statistics
num_drc_runs = 0
num_lvs_runs = 0
@ -96,13 +95,24 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
f.write("gds warning default\n")
# Flatten the transistors
# Bug in Netgen 1.5.194 when using this...
f.write("gds flatglob *_?mos_m*\n")
try:
from tech import blackbox_cells
except ImportError:
blackbox_cells = []
try:
from tech import flatglob
except ImportError:
flatglob = []
f.write("gds readonly true\n")
for entry in flatglob:
f.write("gds flatglob " +entry + "\n")
# These two options are temporarily disabled until Tim fixes a bug in magic related
# to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
# they appear to be disconnected.
f.write("gds flatten true\n")
f.write("gds ordering true\n")
f.write("gds readonly true\n")
f.write("gds read {}\n".format(gds_name))
f.write('puts "Finished reading gds {}"\n'.format(gds_name))
f.write("load {}\n".format(cell_name))
@ -164,10 +174,6 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
f.write("#!/bin/sh\n")
f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH']))
# Copy the bitcell mag files if they exist
try:
from tech import blackbox_cells
except ImportError:
blackbox_cells = []
for blackbox_cell_name in blackbox_cells:
mag_file = OPTS.openram_tech + "maglef_lib/" + blackbox_cell_name + ".mag"
debug.check(os.path.isfile(mag_file), "Could not find blackbox cell {}".format(mag_file))

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@ -90,8 +90,8 @@ class sky130_replica_column(sky130_bitcell_base_array):
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
self.add_pin("top_gate", "INPUT")
self.add_pin("bot_gate", "INPUT")
#self.add_pin("top_gate", "INPUT")
#self.add_pin("bot_gate", "INPUT")
def add_modules(self):
self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
@ -220,6 +220,16 @@ class sky130_replica_column(sky130_bitcell_base_array):
width=self.width,
height=wl_pin.height())
# for colend in [self.cell_inst[0], self.cell_inst[self.row_size]]:
# inst = self.cell_inst[row]
# for pin_name in ["top_gate", "bot_gate"]:
# pin = inst.get_pin("gate")
# self.add_layout_pin(text=pin_name,
# layer=pin.layer,
# offset=pin.ll(),
# width=pin.width(),
# height=pin.height())
for row in range(self.row_size + 2):
inst = self.cell_inst[row]
# add only 1 label per col
@ -235,7 +245,6 @@ class sky130_replica_column(sky130_bitcell_base_array):
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
print("welling")
try:
from tech import layer_override
if layer_override['VNB']:

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@ -781,6 +781,16 @@ library_prefix_name = "sky130_fd_bd_sram__"
# List of cells to skip running DRC/LVS on directly
# This will look for a maglef file and copy it over the mag file
# before DRC after extraction
flatglob = ["*_?mos_m*",
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_cell",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell",
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_cell",
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs"]
blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
"sky130_fd_bd_sram__openram_dp_cell_dummy",
"sky130_fd_bd_sram__openram_dp_cell_replica",