mirror of https://github.com/VLSIDA/OpenRAM.git
add flatglob to tech file; sky130 replica col lvs working
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@ -26,7 +26,6 @@ import shutil
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import debug
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from globals import OPTS
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from .run_script import *
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# Keep track of statistics
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num_drc_runs = 0
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num_lvs_runs = 0
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@ -96,13 +95,24 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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f.write("gds warning default\n")
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# Flatten the transistors
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# Bug in Netgen 1.5.194 when using this...
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f.write("gds flatglob *_?mos_m*\n")
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try:
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from tech import blackbox_cells
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except ImportError:
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blackbox_cells = []
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try:
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from tech import flatglob
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except ImportError:
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flatglob = []
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f.write("gds readonly true\n")
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for entry in flatglob:
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f.write("gds flatglob " +entry + "\n")
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# These two options are temporarily disabled until Tim fixes a bug in magic related
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# to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
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# they appear to be disconnected.
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f.write("gds flatten true\n")
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f.write("gds ordering true\n")
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f.write("gds readonly true\n")
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f.write("gds read {}\n".format(gds_name))
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f.write('puts "Finished reading gds {}"\n'.format(gds_name))
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f.write("load {}\n".format(cell_name))
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@ -164,10 +174,6 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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f.write("#!/bin/sh\n")
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f.write('export OPENRAM_TECH="{}"\n'.format(os.environ['OPENRAM_TECH']))
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# Copy the bitcell mag files if they exist
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try:
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from tech import blackbox_cells
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except ImportError:
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blackbox_cells = []
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for blackbox_cell_name in blackbox_cells:
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mag_file = OPTS.openram_tech + "maglef_lib/" + blackbox_cell_name + ".mag"
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debug.check(os.path.isfile(mag_file), "Could not find blackbox cell {}".format(mag_file))
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@ -90,8 +90,8 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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self.add_pin("top_gate", "INPUT")
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self.add_pin("bot_gate", "INPUT")
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#self.add_pin("top_gate", "INPUT")
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#self.add_pin("bot_gate", "INPUT")
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def add_modules(self):
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self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
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@ -220,6 +220,16 @@ class sky130_replica_column(sky130_bitcell_base_array):
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width=self.width,
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height=wl_pin.height())
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# for colend in [self.cell_inst[0], self.cell_inst[self.row_size]]:
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# inst = self.cell_inst[row]
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# for pin_name in ["top_gate", "bot_gate"]:
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# pin = inst.get_pin("gate")
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# self.add_layout_pin(text=pin_name,
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# layer=pin.layer,
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# offset=pin.ll(),
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# width=pin.width(),
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# height=pin.height())
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for row in range(self.row_size + 2):
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inst = self.cell_inst[row]
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# add only 1 label per col
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@ -235,7 +245,6 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
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print("welling")
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try:
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from tech import layer_override
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if layer_override['VNB']:
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@ -781,6 +781,16 @@ library_prefix_name = "sky130_fd_bd_sram__"
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# List of cells to skip running DRC/LVS on directly
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# This will look for a maglef file and copy it over the mag file
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# before DRC after extraction
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flatglob = ["*_?mos_m*",
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"sky130_fd_bd_sram__sram_sp_cell_fom_serifs",
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"sky130_fd_bd_sram__openram_sp_cell_opt1a_cell",
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"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
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"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell",
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"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce",
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"sky130_fd_bd_sram__openram_sp_cell_opt1a_cell",
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"sky130_fd_bd_sram__sram_sp_cell_fom_serifs"]
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blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
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"sky130_fd_bd_sram__openram_dp_cell_dummy",
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"sky130_fd_bd_sram__openram_dp_cell_replica",
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