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fix drc error in wlen_row

This commit is contained in:
samuelkcrow 2022-07-19 17:57:19 -07:00
parent 08ac1c176a
commit 5fa0689c02
2 changed files with 2 additions and 2 deletions
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2
compiler/modules/control_logic_delay.py
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@ -573,7 +573,7 @@ class control_logic_delay(design.design):
out_pos = out_pin.center()
in_pin = self.wl_en_driver_inst.get_pin("A")
in_pos = in_pin.center()
mid1 = vector(in_pos.x, out_pos.y)
mid1 = vector(out_pos.x, in_pos.y)
self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
self.add_via_stack_center(from_layer=out_pin.layer,
to_layer=in_pin.layer,

2
compiler/modules/multi_delay_chain.py
View File

@ -206,7 +206,7 @@ class multi_delay_chain(design.design):
# It gets routed down a bit to prevent overlapping adjacent
# M3 when connecting to vertical bus
a_pin = self.driver_inst_list[0].get_pin("A")
mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch) # Not 100% sure correct
mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch)
self.add_via_stack_center(from_layer=a_pin.layer,
to_layer="m3",
offset=mid_loc)