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use spice names for delay chain output pins in layout

This commit is contained in:
samuelkcrow 2022-07-18 12:32:12 -07:00
parent 73021be8eb
commit 12c58b0457
2 changed files with 5 additions and 5 deletions
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5
compiler/modules/control_logic_delay.py
View File

@ -394,7 +394,10 @@ class control_logic_delay(design.design):
self.delay_inst.place(offset, mirror="MX")
def route_delay(self):
delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \
# this is a bit of a hack because I would prefer to just name these pins delay in the layout
# instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py
out_pins = ["out{}".format(str(pin)) for pin in self.multi_delay_chain.pinout_list]
delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \
["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
self.connect_vertical_bus(delay_map,

5
compiler/modules/multi_delay_chain.py
View File

@ -216,8 +216,6 @@ class multi_delay_chain(design.design):
layer="m3",
offset=mid_loc)
delay_index = 1
for pin_number in self.pinout_list:
# pin is A pin of right-most load/fanout inverter
output_driver_inst = self.driver_inst_list[pin_number - 1]
@ -225,7 +223,6 @@ class multi_delay_chain(design.design):
self.add_via_stack_center(from_layer=a_pin.layer,
to_layer="m3",
offset=a_pin.center())
self.add_layout_pin_rect_center(text="delay{}".format(str(delay_index)),
self.add_layout_pin_rect_center(text="out{}".format(str(pin_number)),
layer="m3",
offset=a_pin.center())
delay_index += 1