mirror of https://github.com/VLSIDA/OpenRAM.git
fix offsets to match original replica array, and make array translation statically sized
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@ -209,6 +209,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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# row-based or column based power and ground lines.
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self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
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self.unused_offset = vector(0.25, 0.25)
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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@ -216,19 +217,14 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the replica array
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self.replica_bitcell_array_inst.place(offset=0)
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self.replica_bitcell_array_inst.place(offset=self.unused_offset)
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self.add_end_caps()
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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# Note that this doesn't include the row/col cap
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self.array_offset = self.bitcell_offset.scale(len(self.left_rbl), self.rbl[0])
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self.translate_all(self.array_offset.scale(-1, -1))
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# shift everything up and right to account for cap cells
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self.translate_all(self.bitcell_offset.scale(-1, -1))
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# Add extra width on the left and right for the unused WLs
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self.width = self.dummy_col_insts[1].rx()
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self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
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self.height = self.dummy_row_insts[1].uy()
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self.add_layout_pins()
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@ -285,12 +281,12 @@ class capped_replica_bitcell_array(bitcell_base_array):
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.rbl[0] + 1) % 2
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dummy_row_offset = self.bitcell_offset.scale(0, flip_dummy - 1)
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dummy_row_offset = self.bitcell_offset.scale(0, flip_dummy - 1) + self.unused_offset
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self.dummy_row_insts[0].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# Far left dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(-1, -1)
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dummy_col_offset = self.bitcell_offset.scale(-1, -1) + self.unused_offset
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self.dummy_col_insts[0].place(offset=dummy_col_offset)
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# Far right dummy col
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