mirror of https://github.com/VLSIDA/OpenRAM.git
remove pre_sen entirely, move inverter to wl_en row, complete placement functions
This commit is contained in:
samuelkcrow
parent
7b4af87fda
commit
0a3c1dd9b8
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@ -112,7 +112,7 @@ class control_logic_delay(design.design):
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# max_fanout = max(self.num_rows, self.num_cols)
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# wl_en drives every row in the bank
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# MRG 9/3/2021: Ensure that this is two stages to prevent race conditions with the write driver
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# this calculation is from the rbl control logic, it may not be optimal in this circuit
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size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)]
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self.wl_en_driver = factory.create(module_type="pdriver",
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size_list=size_list,
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@ -120,7 +120,7 @@ class control_logic_delay(design.design):
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# wl_en_unbuf is the weak timing signal that feeds wl_en_driver
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self.wl_en_and = factory.create(module_type="pand2",
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size=1, # FIXME: Minimum size??? Should even have this gate??
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size=1,
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height=dff_height)
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# w_en drives every write driver
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@ -297,7 +297,6 @@ class control_logic_delay(design.design):
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self.create_gated_clk_buf_row()
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self.create_delay()
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self.create_glitches()
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self.create_pre_sen_invs()
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_wen_row()
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@ -335,16 +334,12 @@ class control_logic_delay(design.design):
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row += 1
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self.place_wlen_row(row)
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row += 1
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self.place_glitch1_row(row)
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row += 1
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self.place_glitch2_row(row)
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row += 1
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self.place_glitch3_row(row)
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row += 1
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self.place_pre_sen_row(row)
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row += 1
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control_center_y = self.pre_sen_inv_inst.uy() + self.m3_pitch
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control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch
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# Delay chain always gets placed at row 4
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self.place_delay(4)
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@ -395,7 +390,7 @@ class control_logic_delay(design.design):
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offset = vector(0, y_off)
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self.delay_inst.place(offset, mirror="MX")
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def route_delay(self): # TODO: this
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def route_delay(self): # TODO
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out_pos = self.delay_inst.get_pin("out").center()
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# Connect to the rail level with the vdd rail
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@ -425,6 +420,8 @@ class control_logic_delay(design.design):
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mod=self.nand2)
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self.connect_inst(["delay2", "delay5", "glitch3_bar", "vdd", "gnd"])
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# glitch1 is placed in place_pen_row()
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def place_glitch2_row(self, row):
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x_offset = self.control_x_offset
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@ -439,12 +436,12 @@ class control_logic_delay(design.design):
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self.row_end_inst.append(self.glitch3_nand_inst)
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def route_glitches(self): # TODO: this
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def route_glitches(self): #TODO
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glitch1_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus)
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self.connect_vertical_bus(wlen_map, self.wl_en_driver_inst, self.input_bus)
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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self.connect_output(self.wl_en_driver_inst, "Z", "wl_en")
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def create_clk_buf_row(self):
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""" Create the multistage and gated clock buffer """
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@ -554,22 +551,23 @@ class control_logic_delay(design.design):
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mod=self.wl_en_and)
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self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
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self.wl_en_inst=self.add_inst(name="buf_wl_en",
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self.wl_en_driver_inst=self.add_inst(name="buf_wl_en",
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mod=self.wl_en_driver)
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self.connect_inst(["wl_en_unbuf", "wl_en", "vdd", "gnd"])
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def place_wlen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.wl_en_inst, x_offset, row)
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x_offset = self.place_util(self.wl_en_unbuf_and_inst, x_offset, row)
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x_offset = self.place_util(self.wl_en_driver_inst, x_offset, row)
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self.row_end_inst.append(self.wl_en_inst)
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self.row_end_inst.append(self.wl_en_driver_inst)
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def route_wlen(self):
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def route_wlen(self): #TODO
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wlen_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus)
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self.connect_vertical_bus(wlen_map, self.wl_en_driver_inst, self.input_bus)
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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self.connect_output(self.wl_en_driver_inst, "Z", "wl_en")
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def create_pen_row(self):
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self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
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@ -584,7 +582,7 @@ class control_logic_delay(design.design):
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self.row_end_inst.append(self.p_en_bar_driver_inst)
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def route_pen(self):
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def route_pen(self): #TODO
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in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"])
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self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus)
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@ -600,34 +598,16 @@ class control_logic_delay(design.design):
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self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar")
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def create_pre_sen_invs(self):
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""" A pair of inverters to create additional signals from and buffer glitch 3"""
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def create_sen_row(self):
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self.glitch3_buf_inv_inst = self.add_inst(name="inv_glitch3_buf",
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mod=self.inv)
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self.connect_inst(["glitch3_bar", "glitch3_buf", "vdd", "gnd"])
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self.pre_sen_inv_inst = self.add_inst(name="inv_pre_sen",
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mod=self.inv)
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self.connect_inst(["glitch3_buf", "pre_sen", "vdd", "gnd"])
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def place_pre_sen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row)
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x_offset = self.place_util(self.pre_sen_inv_inst, x_offset, row)
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self.row_end_inst.append(self.pre_sen_inv_inst)
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def route_pre_sen(self): #TODO: this
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pass
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def create_sen_row(self):
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""" Create the sense enable buffer. """
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if self.port_type=="rw":
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input_name = "we_bar"
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else:
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input_name = "cs"
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# GATE FOR S_EN
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self.s_en_gate_inst = self.add_inst(name="and_s_en",
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mod=self.sen_and3)
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self.connect_inst(["glitch3_bar", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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@ -635,11 +615,12 @@ class control_logic_delay(design.design):
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def place_sen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row)
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x_offset = self.place_util(self.s_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.s_en_gate_inst)
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def route_sen(self):
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def route_sen(self): #TODO
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if self.port_type=="rw":
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input_name = "we_bar"
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@ -653,17 +634,13 @@ class control_logic_delay(design.design):
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def create_wen_row(self):
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# input: we (or cs) output: w_en
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if self.port_type == "rw":
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input_name = "we"
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else:
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# No we for write-only ports, so use cs
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input_name = "cs"
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# GATE THE W_EN
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self.w_en_gate_inst = self.add_inst(name="and_w_en",
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mod=self.wen_and)
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# Only drive the writes in the second half of the clock cycle during a write operation.
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self.connect_inst([input_name, "glitch2_bar", "glitch3_buf", "w_en", "vdd", "gnd"])
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def place_wen_row(self, row):
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@ -673,11 +650,10 @@ class control_logic_delay(design.design):
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self.row_end_inst.append(self.w_en_gate_inst)
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def route_wen(self):
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def route_wen(self): #TODO
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if self.port_type == "rw":
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input_name = "we"
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else:
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# No we for write-only ports, so use cs
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input_name = "cs"
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wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"])
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