Change is_unit_test to False by default

compiler/globals.py

@@ -185,7 +185,7 @@ def check_versions():
         OPTS.coverage = 0
 
 
-def init_openram(config_file, is_unit_test=True):
+def init_openram(config_file, is_unit_test=False):
     """ Initialize the technology, paths, simulators, etc. """
 
     check_versions()
@@ -294,7 +294,7 @@ def get_tool(tool_type, preferences, default_name=None):
             return(None, "")
 
 
-def read_config(config_file, is_unit_test=True):
+def read_config(config_file, is_unit_test=False):
     """
     Read the configuration file that defines a few parameters. The
     config file is just a Python file that defines some config

compiler/tests/01_library_test.py

@@ -18,7 +18,7 @@ class library_lvs_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import verify
 
         (gds_dir, sp_dir, allnames) = setup_files()

compiler/tests/03_contact_test.py

@@ -19,7 +19,7 @@ class contact_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         from tech import active_stack, poly_stack, beol_stacks
 

compiler/tests/03_path_test.py

@@ -18,7 +18,7 @@ class path_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from base import wire_path
         import tech
         from base import design

compiler/tests/03_ptx_1finger_nmos_test.py

@@ -20,7 +20,7 @@ class ptx_1finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking min size NMOS with 1 finger")

compiler/tests/03_ptx_1finger_pmos_test.py

@@ -19,7 +19,7 @@ class ptx_1finger_pmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking min size PMOS with 1 finger")

compiler/tests/03_ptx_3finger_nmos_test.py

@@ -19,7 +19,7 @@ class ptx_3finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers NMOS")

compiler/tests/03_ptx_3finger_pmos_test.py

@@ -19,7 +19,7 @@ class ptx_3finger_pmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers PMOS")

compiler/tests/03_ptx_4finger_nmos_test.py

@@ -19,7 +19,7 @@ class ptx_4finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers NMOS")

compiler/tests/03_ptx_4finger_pmos_test.py

@@ -19,7 +19,7 @@ class ptx_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers PMOS")

compiler/tests/03_ptx_no_contacts_test.py

@@ -20,7 +20,7 @@ class ptx_no_contacts_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking single finger no source/drain")

compiler/tests/03_wire_test.py

@@ -18,7 +18,7 @@ class wire_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from base import wire
         import tech
         from base import design

compiler/tests/04_and2_dec_test.py

@@ -20,7 +20,7 @@ class and2_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 

compiler/tests/04_and3_dec_test.py

@@ -20,7 +20,7 @@ class and3_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 

compiler/tests/04_and4_dec_test.py

@@ -21,7 +21,7 @@ class and4_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 

compiler/tests/04_column_mux_1rw_1r_test.py

@@ -20,7 +20,7 @@ class column_mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/04_column_mux_pbitcell_test.py

@@ -20,7 +20,7 @@ class column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux in multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/04_column_mux_test.py

@@ -20,7 +20,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux in single port
         debug.info(2, "Checking column mux")

compiler/tests/04_dff_buf_test.py

@@ -20,7 +20,7 @@ class dff_buf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         debug.info(2, "Testing dff_buf 4x 8x")
         a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
         self.local_check(a)

compiler/tests/04_dummy_pbitcell_test.py

@@ -19,7 +19,7 @@ class replica_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import dummy_pbitcell
 
         OPTS.bitcell = "pbitcell"

compiler/tests/04_pand2_test.py

@@ -19,7 +19,7 @@ class pand2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 

compiler/tests/04_pand3_test.py

@@ -19,7 +19,7 @@ class pand3_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 

compiler/tests/04_pand4_test.py

@@ -19,7 +19,7 @@ class pand4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 

compiler/tests/04_pbitcell_test.py

@@ -20,7 +20,7 @@ class pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports=1
         OPTS.num_w_ports=1

compiler/tests/04_pbuf_dec_8x_test.py

@@ -19,7 +19,7 @@ class pbuf_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/04_pbuf_test.py

@@ -19,7 +19,7 @@ class pbuf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing buffer 8x")
         a = factory.create(module_type="pbuf", size=8)

compiler/tests/04_pdriver_test.py

@@ -19,7 +19,7 @@ class pdriver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         # a tests the error message for specifying conflicting conditions

compiler/tests/04_pinv_100x_test.py

@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 100x inverter")
         tx = factory.create(module_type="pinv", size=100)

compiler/tests/04_pinv_10x_test.py

@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 8x inverter")
         tx = factory.create(module_type="pinv", size=8)

compiler/tests/04_pinv_1x_beta_test.py

@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 1x beta=3 size inverter")
         tx = factory.create(module_type="pinv", size=1, beta=3)

compiler/tests/04_pinv_1x_test.py

@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 1x size inverter")
         tx = factory.create(module_type="pinv", size=1)

compiler/tests/04_pinv_2x_test.py

@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2x size inverter")
         tx = factory.create(module_type="pinv", size=2)

compiler/tests/04_pinv_dec_1x_test.py

@@ -20,7 +20,7 @@ class pinv_dec_1x_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/04_pinvbuf_test.py

@@ -19,7 +19,7 @@ class pinvbuf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         a = factory.create(module_type="pinvbuf", size=8)

compiler/tests/04_pnand2_test.py

@@ -19,7 +19,7 @@ class pnand2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2-input nand gate")
         tx = factory.create(module_type="pnand2", size=1)

compiler/tests/04_pnand3_test.py

@@ -19,7 +19,7 @@ class pnand3_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 3-input nand gate")
         tx = factory.create(module_type="pnand3", size=1)

compiler/tests/04_pnand4_test.py

@@ -20,7 +20,7 @@ class pnand4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 4-input nand gate")
         tx = factory.create(module_type="pnand4", size=1)

compiler/tests/04_pnor2_test.py

@@ -19,7 +19,7 @@ class pnor2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2-input nor gate")
         tx = factory.create(module_type="pnor2", size=1)

compiler/tests/04_precharge_1rw_1r_test.py

@@ -20,7 +20,7 @@ class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge array in multi-port
         OPTS.num_rw_ports = 1

compiler/tests/04_precharge_pbitcell_test.py

@@ -19,7 +19,7 @@ class precharge_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge in multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/04_precharge_test.py

@@ -20,7 +20,7 @@ class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge in single port
         debug.info(2, "Checking precharge for handmade bitcell")

compiler/tests/04_pwrite_driver_test.py

@@ -20,7 +20,7 @@ import debug
 class pwrite_driver_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name), is_unit_test=True)
 
         debug.info(2, "Checking 1x pwrite_driver")
         tx = factory.create(module_type="pwrite_driver", size=1)

compiler/tests/04_replica_pbitcell_test.py

@@ -19,7 +19,7 @@ class replica_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import replica_pbitcell
 
         OPTS.bitcell = "pbitcell"

compiler/tests/04_wordline_driver_test.py

@@ -21,7 +21,7 @@ class wordline_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")

compiler/tests/05_bitcell_array_1rw_1r_test.py

@@ -20,7 +20,7 @@ class bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/05_bitcell_array_test.py

@@ -20,7 +20,7 @@ class array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 8x8 array for 6t_cell")
 

compiler/tests/05_dummy_array_test.py

@@ -17,7 +17,7 @@ class dummy_row_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dummy row for 6t_cell")
         a = factory.create(module_type="dummy_array", rows=1, cols=4)

compiler/tests/05_pbitcell_array_test.py

@@ -20,7 +20,7 @@ class pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"

compiler/tests/06_column_decoder_16row_test.py

@@ -20,7 +20,7 @@ class column_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_132row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_16row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_17row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_32row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_4096row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_512row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_decoder_64row_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -20,7 +20,7 @@ class hierarchical_decoder_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         # check hierarchical decoder for multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0

compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # checking hierarchical precode 2x4 for multi-port
         OPTS.num_rw_ports = 1

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")

compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # checking hierarchical precode 3x8 for multi-port
         OPTS.num_rw_ports = 1

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")

compiler/tests/06_hierarchical_predecode4x16_test.py

@@ -20,7 +20,7 @@ class hierarchical_predecode4x16_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1

compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/07_column_mux_array_16mux_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 16-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=64, word_size=4)

compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/07_column_mux_array_2mux_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 2-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=8)

compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/07_column_mux_array_4mux_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 4-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=4)

compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/07_column_mux_array_8mux_test.py

@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 8-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=32, word_size=4)

compiler/tests/07_column_mux_array_pbitcell_test.py

@@ -19,7 +19,7 @@ class column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux array in multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/08_precharge_array_1rw_1r_test.py

@@ -20,7 +20,7 @@ class precharge_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge array in multi-port
         OPTS.num_rw_ports = 1

compiler/tests/08_precharge_array_test.py

@@ -19,7 +19,7 @@ class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 3 column precharge")
         pc = factory.create(module_type="precharge_array", columns=3)

compiler/tests/08_wordline_buffer_array_test.py

@@ -20,7 +20,7 @@ class wordline_buffer_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")

compiler/tests/08_wordline_driver_array_1rw_1r_test.py

@@ -20,7 +20,7 @@ class wordline_driver_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1

compiler/tests/08_wordline_driver_array_pbitcell_test.py

@@ -20,7 +20,7 @@ class wordline_driver_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/08_wordline_driver_array_test.py

@@ -20,7 +20,7 @@ class wordline_driver_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")

compiler/tests/09_sense_amp_array_1rw_1r_test.py

@@ -20,7 +20,7 @@ class sense_amp_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/09_sense_amp_array_pbitcell_test.py

@@ -19,7 +19,7 @@ class sense_amp_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         #check sense amp array for multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/09_sense_amp_array_spare_cols_test.py

@@ -19,7 +19,7 @@ class sense_amp_array_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check sense amp array for single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3")

compiler/tests/09_sense_amp_array_test.py

@@ -19,7 +19,7 @@ class sense_amp_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)

compiler/tests/10_write_driver_array_1rw_1r_test.py

@@ -20,7 +20,7 @@ class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/10_write_driver_array_pbitcell_test.py

@@ -19,7 +19,7 @@ class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/10_write_driver_array_spare_cols_test.py

@@ -19,7 +19,7 @@ class write_driver_array_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3")

compiler/tests/10_write_driver_array_test.py

@@ -19,7 +19,7 @@ class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")

compiler/tests/10_write_driver_array_wmask_pbitcell_test.py

@@ -21,7 +21,7 @@ class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/10_write_driver_array_wmask_spare_cols_test.py

@@ -21,7 +21,7 @@ class write_driver_array_wmask_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")

compiler/tests/10_write_driver_array_wmask_test.py

@@ -21,7 +21,7 @@ class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")

compiler/tests/10_write_mask_and_array_1rw_1r_test.py

@@ -20,7 +20,7 @@ class write_mask_and_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/10_write_mask_and_array_pbitcell_test.py

@@ -21,7 +21,7 @@ class write_mask_and_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"

compiler/tests/10_write_mask_and_array_test.py

@@ -21,7 +21,7 @@ class write_mask_and_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")