Added conditional sections to template

compiler/tests/sram_1b_16_1rw_scn4m_subm.log

@@ -1,2 +0,0 @@
-ERROR: file magic.py: line 358: sram	LVS mismatch (results in /tmp/openram_bugra_12868_temp/sram.lvs.report)
-

compiler/tests/sram_1b_16_1rw_sky130.log

@@ -1,3 +0,0 @@
-ERROR: file design.py: line 47: Custom cell pin names do not match spice file:
-['D', 'Q', 'CLK', 'VDD', 'GND'] vs []
-

compiler/verilog_template/template.py

@@ -25,7 +25,6 @@ class loopSection(baseSection):
     """
 
     def __init__(self, var, key):
-        self.children = []
         self.var = var
         self.key = key
 

compiler/verilog_template/test.py

@@ -1,20 +0,0 @@
-from template import template
-
-dict = {
-        'module_name': 'sram_1kbyte_32b_2bank', 
-        'bank_module_name': 'sram_1kbyte_32b_2bank_1bank', 
-        'vdd': 'vdd', 
-        'gnd': 'gnd', 
-        'ports': [0, 1], 
-        'rw_ports': [0], 
-        'r_ports': [1], 
-        'w_ports': [],
-        'banks': [0, 1],
-        'data_width': 32, 
-        'addr_width': 8,
-        'bank_sel': 1,
-        'num_wmask': 4
-        }
-t = template('../sram/sram_multibank_template.v', dict)
-t.write(dict['module_name'] + '.v')
-