use cs_buf for sense amp on r ports instead of cs

2022-05-04 12:51:31 -07:00 · 2022-05-04 12:51:31 -07:00 · 45239ca2a9
parent c4138c9f9b
commit 45239ca2a9
1 changed files with 1 additions and 1 deletions
--- a/compiler/modules/control_logic_delay.py
+++ b/compiler/modules/control_logic_delay.py
@ -617,7 +617,7 @@ class control_logic_delay(design.design):
        if self.port_type=="rw":
            input_name = "we_bar"
        else:
-            input_name = "cs"
+            input_name = "cs_buf"
        # GATE FOR S_EN
        self.s_en_gate_inst = self.add_inst(name="and_s_en",
                                            mod=self.sen_and3)