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revert variable names to those inherited from bitcell base array

This commit is contained in:
samuelkcrow 2023-02-07 11:32:02 -08:00
parent 2948b08e66
commit 8d6d8f2f8c
3 changed files with 45 additions and 46 deletions
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41
compiler/modules/capped_replica_bitcell_array.py
View File

@ -155,34 +155,31 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_pin("gnd", "GROUND")
def add_bitline_pins(self):
# some of these are just included for compatibility with modules instantiating this module
self.bitcell_bitline_names = self.replica_bitcell_array.bitcell_bitline_names
self.all_bitcell_bitline_names = self.replica_bitcell_array.all_bitcell_bitline_names
# these four are only included for compatibility with other modules
self.bitline_names = self.replica_bitcell_array.bitline_names
self.all_bitline_names = self.replica_bitcell_array.all_bitline_names
self.rbl_bitline_names = self.replica_bitcell_array.rbl_bitline_names
self.all_rbl_bitline_names = self.replica_bitcell_array.all_rbl_bitline_names
self.bitline_names = self.replica_bitcell_array.bitline_names
self.all_bitline_names = self.replica_bitcell_array.all_bitline_names
self.add_pin_list(self.all_bitline_names, "INOUT")
# this one is actually used (obviously)
self.bitline_pin_list = self.replica_bitcell_array.bitline_pin_list
self.add_pin_list(self.bitline_pin_list, "INOUT")
def add_wordline_pins(self):
# some of these are just included for compatibility with modules instantiating this module
self.rbl_wordline_names = self.replica_bitcell_array.rbl_wordline_names
self.all_rbl_wordline_names = self.replica_bitcell_array.all_rbl_wordline_names
self.bitcell_wordline_names = self.replica_bitcell_array.wordline_names
self.all_bitcell_wordline_names = self.replica_bitcell_array.all_wordline_names
self.wordline_names = self.replica_bitcell_array.wordline_names
self.all_wordline_names = self.replica_bitcell_array.all_wordline_names
self.used_wordline_names = self.replica_bitcell_array.used_wordline_names
self.unused_wordline_names = self.replica_bitcell_array.unused_wordline_names
self.replica_array_wordline_names = self.replica_bitcell_array.all_wordline_names
self.replica_array_all_wordline_names = self.replica_bitcell_array.wordline_names
self.replica_array_wordline_names_with_grounded_wls = ["gnd" if x in self.unused_wordline_names else x for x in self.replica_array_wordline_names]
self.replica_array_wordline_names_with_grounded_wls = ["gnd" if x in self.unused_wordline_names else x for x in self.replica_bitcell_array.wordline_pin_list]
self.all_wordline_names = []
self.all_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
self.all_wordline_names.extend(self.replica_array_wordline_names_with_grounded_wls)
self.all_wordline_names.extend(["gnd"] * len(self.col_cap_bottom.get_wordline_names()))
self.wordline_pin_list = []
self.wordline_pin_list.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
self.wordline_pin_list.extend(self.replica_array_wordline_names_with_grounded_wls)
self.wordline_pin_list.extend(["gnd"] * len(self.col_cap_bottom.get_wordline_names()))
self.add_pin_list(self.used_wordline_names, "INPUT")
@ -193,25 +190,25 @@ class capped_replica_bitcell_array(bitcell_base_array):
# Main array
self.replica_bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
mod=self.replica_bitcell_array)
self.connect_inst(self.all_bitline_names + self.replica_array_wordline_names_with_grounded_wls + self.supplies)
self.connect_inst(self.bitline_pin_list + self.replica_array_wordline_names_with_grounded_wls + self.supplies)
# Top/bottom dummy rows or col caps
self.dummy_row_insts = []
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
mod=self.col_cap_bottom))
self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies)
self.connect_inst(self.bitline_pin_list + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies)
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
mod=self.col_cap_top))
self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies)
self.connect_inst(self.bitline_pin_list + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies)
# Left/right Dummy columns
self.dummy_col_insts = []
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
mod=self.row_cap_left))
self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.all_wordline_names + self.supplies)
self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.wordline_pin_list + self.supplies)
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
mod=self.row_cap_right))
self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.all_wordline_names + self.supplies)
self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.wordline_pin_list + self.supplies)
# bitcell array needed for some offset calculations
self.bitcell_array_inst = self.replica_bitcell_array.bitcell_array_inst
@ -313,7 +310,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.dummy_col_insts[1].place(offset=dummy_col_offset)
def add_layout_pins(self):
for pin_name in self.used_wordline_names + self.all_bitline_names:
for pin_name in self.used_wordline_names + self.bitline_pin_list:
pin = self.replica_bitcell_array_inst.get_pin(pin_name)
if "wl" in pin_name:

8
compiler/modules/local_bitcell_array.py
View File

@ -94,11 +94,11 @@ class local_bitcell_array(bitcell_base_array):
# Inputs to the bitcell array (by port)
self.array_wordline_inputs = []
self.wordline_names = self.bitcell_array.bitcell_wordline_names
self.all_wordline_names = self.bitcell_array.all_bitcell_wordline_names
self.wordline_names = self.bitcell_array.wordline_names
self.all_wordline_names = self.bitcell_array.all_wordline_names
self.bitline_names = self.bitcell_array.bitcell_bitline_names
self.all_bitline_names = self.bitcell_array.all_bitcell_bitline_names
self.bitline_names = self.bitcell_array.bitline_names
self.all_bitline_names = self.bitcell_array.all_bitline_names
self.rbl_wordline_names = self.bitcell_array.rbl_wordline_names
self.all_rbl_wordline_names = self.bitcell_array.all_rbl_wordline_names

42
compiler/modules/replica_bitcell_array.py
View File

@ -157,18 +157,18 @@ class replica_bitcell_array(bitcell_base_array):
# Make a flat list too
self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
self.bitcell_bitline_names = self.bitcell_array.bitline_names
self.bitline_names = self.bitcell_array.bitline_names
# Make a flat list too
self.all_bitcell_bitline_names = [x for sl in zip(*self.bitcell_bitline_names) for x in sl]
self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
self.all_bitline_names = []
self.bitline_pin_list = []
for port in self.left_rbl:
self.all_bitline_names.extend(self.rbl_bitline_names[port])
self.all_bitline_names.extend(self.all_bitcell_bitline_names)
self.bitline_pin_list.extend(self.rbl_bitline_names[port])
self.bitline_pin_list.extend(self.all_bitline_names)
for port in self.right_rbl:
self.all_bitline_names.extend(self.rbl_bitline_names[port])
self.bitline_pin_list.extend(self.rbl_bitline_names[port])
self.add_pin_list(self.all_bitline_names, "INOUT")
self.add_pin_list(self.bitline_pin_list, "INOUT")
def add_wordline_pins(self):
# Unused wordlines are connected to ground at the next level of hierarchy
@ -182,23 +182,25 @@ class replica_bitcell_array(bitcell_base_array):
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
self.bitcell_wordline_names = self.bitcell_array.wordline_names
self.all_bitcell_wordline_names = self.bitcell_array.all_wordline_names
# All wordlines including RBL self.all_wordline_names = []
self.wordline_names = self.bitcell_array.wordline_names
self.all_wordline_names = self.bitcell_array.all_wordline_names
# All wordlines including RBL
self.wordline_pin_list = []
for bit in range(self.rbl[0]):
self.all_wordline_names.extend(self.rbl_wordline_names[bit])
self.all_wordline_names.extend(self.all_bitcell_wordline_names)
self.wordline_pin_list.extend(self.rbl_wordline_names[bit])
self.wordline_pin_list.extend(self.all_wordline_names)
for bit in range(self.rbl[1]):
self.all_wordline_names.extend(self.rbl_wordline_names[self.rbl[0] + bit])
self.wordline_pin_list.extend(self.rbl_wordline_names[self.rbl[0] + bit])
self.used_wordline_names = []
for port in range(self.rbl[0]):
self.used_wordline_names.append(self.rbl_wordline_names[port][port])
self.used_wordline_names.extend(self.all_bitcell_wordline_names)
self.used_wordline_names.extend(self.all_wordline_names)
for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
self.used_wordline_names.append(self.rbl_wordline_names[port][port])
self.add_pin_list(self.all_wordline_names, "INPUT")
self.add_pin_list(self.wordline_pin_list, "INPUT")
def create_instances(self):
""" Create the module instances used in this design """
@ -207,7 +209,7 @@ class replica_bitcell_array(bitcell_base_array):
# Main array
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
mod=self.bitcell_array)
self.connect_inst(self.all_bitcell_bitline_names + self.all_bitcell_wordline_names + self.supplies)
self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
# Replica columns
self.replica_col_insts = []
@ -215,7 +217,7 @@ class replica_bitcell_array(bitcell_base_array):
if port in self.rbls:
self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
mod=self.replica_columns[port]))
self.connect_inst(self.rbl_bitline_names[port] + self.all_wordline_names + self.supplies)
self.connect_inst(self.rbl_bitline_names[port] + self.wordline_pin_list + self.supplies)
else:
self.replica_col_insts.append(None)
@ -225,7 +227,7 @@ class replica_bitcell_array(bitcell_base_array):
for port in self.all_ports: # TODO: tie to self.rbl or whatever
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
mod=self.dummy_row))
self.connect_inst(self.all_bitcell_bitline_names + self.rbl_wordline_names[port] + self.supplies)
self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies)
def create_layout(self):
@ -330,7 +332,7 @@ class replica_bitcell_array(bitcell_base_array):
# All wordlines
# Main array wl
for pin_name in self.all_bitcell_wordline_names:
for pin_name in self.all_wordline_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name)
for pin in pin_list:
self.add_layout_pin(text=pin_name,
@ -351,7 +353,7 @@ class replica_bitcell_array(bitcell_base_array):
height=pin.height())
# Main array bl/br
for pin_name in self.all_bitcell_bitline_names:
for pin_name in self.all_bitline_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name)
for pin in pin_list:
self.add_layout_pin(text=pin_name,