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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl

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samuelkcrow 2022-12-14 08:13:08 -08:00
parent 119bcb9197 7ddb1a39dc
commit 6a8a76dd23
565 changed files with 6175 additions and 3970 deletions
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27
.github/ISSUE_TEMPLATE/bug_report.md vendored Normal file
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@ -0,0 +1,27 @@
---
name: Bug report
about: Create a report to help us improve
title: ''
labels: ''
assignees: ''
---
**Describe the bug**
A clear and concise description of what the bug is.
**Version**
Which commit are you using?
**To Reproduce**
What did you do to demonstrate the bug?
Please include your configuration file used.
**Expected behavior**
A clear and concise description of what you expected to happen.
**Logs**
If applicable, add logs or output to help explain your problem.
**Additional context**
Add any other context about the problem here.

3
.github/workflows/ci.yml vendored
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@ -6,6 +6,9 @@ jobs:
steps:
- name: Checkout code
uses: actions/checkout@v1
- name: Library build
run: |
make library
- name: Docker build
run: |
cd ${{ github.workspace }}/docker

7
.gitignore vendored
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@ -14,5 +14,10 @@ technology/sky130/*_lib
technology/sky130/tech/.magicrc
.idea
compiler/tests/results/
sky*/
open_pdks/
dist/
openram.egg-info/
sky130A/
sky130B/
skywater-pdk/
sky130_fd_bd_sram/

117
HINTS.md
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@ -1,117 +0,0 @@
# Debugging
When OpenRAM runs, it puts files in a temporary directory that is
shown in the banner at the top. Like:
```
/tmp/openram_mrg_18128_temp/
```
This is where simulations and DRC/LVS get run so there is no network
traffic. The directory name is unique for each person and run of
OpenRAM to not clobber any files and allow simultaneous runs. If it
passes, the files are deleted. If it fails, you will see these files:
+ temp.gds is the layout (.mag files too if using SCMOS)
+ temp.sp is the netlist
+ test1.drc.err is the std err output of the DRC command
+ test1.drc.out is the standard output of the DRC command
+ test1.drc.results is the DRC results file
+ test1.lvs.err is the std err output of the LVS command
+ test1.lvs.out is the standard output of the LVS command
+ test1.lvs.results is the DRC results file
Depending on your DRC/LVS tools, there will also be:
+ \_calibreDRC.rul\_ is the DRC rule file (Calibre)
+ dc_runset is the command file (Calibre)
+ extracted.sp (Calibre)
+ run_lvs.sh is a Netgen script for LVS (Netgen)
+ run_drc.sh is a Magic script for DRC (Magic)
+ <topcell>.spice (Magic)
If DRC/LVS fails, the first thing is to check if it ran in the .out and
.err file. This shows the standard output and error output from
running DRC/LVS. If there is a setup problem it will be shown here.
If DRC/LVS runs, but doesn't pass, you then should look at the .results
file. If the DRC fails, it will typically show you the command that was used
to run Calibre or Magic+Netgen.
To debug, you will need a layout viewer. I prefer to use Glade
on my Mac, but you can also use Calibre, Magic, etc.
1. Klayout
You can view the designs in [Klayout](https://www.klayout.de/) with the configuration
file provided in the tech directories. For example,
```
klayout temp.gds -l /home/vagrant/openram/technology/freepdk45/tf/FreePDK45.lyp
```
2. Calibre
Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file:
```
calibredrv temp.gds
```
Select Verification->Start RVE and select the results database file in
the new form (e.g., test1.drc.db). This will start the RVE (results
viewer). Scroll through the check pane and find the DRC check with an
error. Select it and it will open some numbers to the right. Double
click on any of the errors in the result browser. These will be
labelled as numbers "1 2 3 4" for example will be 4 DRC errors.
In the viewer ">" opens the layout down a level.
3. Glade
You can view errors in [Glade](http://www.peardrop.co.uk/glade/) as well.
To remote display over X windows, you need to disable OpenGL acceleration or use vnc
or something. You can disable by adding this to your .bashrc in bash:
```
export GLADE_USE_OPENGL=no
```
or in .cshrc/.tcshrc in csh/tcsh:
```
setenv GLADE_USE_OPENGAL no
```
To use this with the FreePDK45 or SCMOS layer views you should use the
tech files. Then create a .glade.py file in your user directory with
these commands to load the technology layers:
```
ui().importCds("default",
"/Users/mrg/techfiles/freepdk45/display.drf",
"/Users/mrg/techfiles/freepdk45/FreePDK45.tf", 1000, 1,
"/Users/mrg/techfiles/freepdk45/layers.map")
```
Obviously, edit the paths to point to your directory. To switch
between processes, you have to change the importCds command (or you
can manually run the command each time you start glade).
To load the errors, you simply do Verify->Import Calibre Errors select
the .results file from Calibre.
4. Magic
Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules
and [Magic](http://opencircuitdesign.com/)
When running DRC or extraction, OpenRAM will load the GDS file, save
the .ext/.mag files, and export an extracted netlist (.spice).
5. It is possible to use other viewers as well, such as:
* [LayoutEditor](http://www.layouteditor.net/)
# Example to output/input .gds layout files from/to Cadence
1. To create your component layouts, you should stream them to
individual gds files using our provided layermap and flatten
cells. For example,
```
strmout -layerMap layers.map -library sram -topCell $i -view layout -flattenVias -flattenPcells -strmFile ../gds_lib/$i.gds
```
2. To stream a layout back into Cadence, do this:
```
strmin -layerMap layers.map -attachTechFileOfLib NCSU\_TechLib\_FreePDK45 -library sram_4_32 -strmFile sram_4_32.gds
```
When you import a gds file, make sure to attach the correct tech lib
or you will get incorrect layers in the resulting library.

24
MANIFEST.in Normal file
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@ -0,0 +1,24 @@
include Makefile
include openram.mk
include setpaths.sh
include requirements.txt
include docker/*
recursive-include compiler *
recursive-include technology *
exclude .DS_Store
exclude .idea
exclude **/model_data
exclude technology/sky130/*_lib
exclude technology/sky130/tech/.magicrc
exclude compiler/gen_stimulus.py
exclude compiler/model_data_util.py
exclude compiler/printGDS.py
exclude compiler/processGDS.py
exclude compiler/uniquifyGDS.py
exclude compiler/view_profile.py
exclude compiler/run_profile.sh
recursive-exclude open_pdks *
recursive-exclude compiler/tests/results *
recursive-exclude technology/freepdk45/ncsu_basekit *
recursive-exclude outputs *
global-exclude *.pyc *~ *.orig *.rej *.aux *.out *.toc *.synctex.gz

29
Makefile
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@ -58,16 +58,14 @@ $(SKY130_PDKS_DIR): check-pdk-root
@echo "Cloning skywater PDK..."
@[ -d $(PDK_ROOT)/skywater-pdk ] || \
git clone https://github.com/google/skywater-pdk.git $(PDK_ROOT)/skywater-pdk
@cd $(SKY130_PDKS_DIR) && \
git checkout main && git pull && \
git checkout -qf $(SKY130_PDKS_GIT_COMMIT) && \
git submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
@git -C $(SKY130_PDKS_DIR) checkout $(SKY130_PDKS_GIT_COMMIT) && \
git -C $(SKY130_PDKS_DIR) submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
$(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR)
@echo "Cloning open_pdks..."
@[ -d $(OPEN_PDKS_DIR) ] || \
git clone $(OPEN_PDKS_GIT_REPO) $(OPEN_PDKS_DIR)
@cd $(OPEN_PDKS_DIR) && git pull && git checkout $(OPEN_PDKS_GIT_COMMIT)
@git -C $(OPEN_PDKS_DIR) checkout $(OPEN_PDKS_GIT_COMMIT)
$(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR)
@echo "Installing open_pdks..."
@ -80,11 +78,11 @@ $(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR)
$(SRAM_LIB_DIR): check-pdk-root
@echo "Cloning SRAM library..."
@[ -d $(SRAM_LIB_DIR) ] || (\
git clone $(SRAM_LIB_GIT_REPO) $(SRAM_LIB_DIR) && \
cd $(SRAM_LIB_DIR) && git pull && git checkout $(SRAM_LIB_GIT_COMMIT))
@[ -d $(SRAM_LIB_DIR) ] || \
git clone $(SRAM_LIB_GIT_REPO) $(SRAM_LIB_DIR)
@git -C $(SRAM_LIB_DIR) checkout $(SRAM_LIB_GIT_COMMIT)
install: $(SRAM_LIB_DIR) pdk
install: $(SRAM_LIB_DIR)
@[ -d $(PDK_ROOT)/sky130A ] || \
(echo "Warning: $(PDK_ROOT)/sky130A not found!! Run make pdk first." && false)
@[ -d $(PDK_ROOT)/skywater-pdk ] || \
@ -215,3 +213,16 @@ wipe: uninstall
@rm -rf $(OPEN_PDKS_DIR)
@rm -rf $(SKY130_PDKS_DIR)
.PHONY: wipe
# Build the openram library
build-library:
@rm -rf dist
@rm -rf openram.egg-info
@python3 -m pip install --upgrade build
@python3 -m build
.PHONY: build-library
# Build and install the openram library
library: build-library
@python3 -m pip install --force --find-links=dist openram
.PHONY: library

181
README.md
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@ -19,169 +19,8 @@ predictive and fabricable technologies.
# Documentation
Please take a look at our presentation We have created a detailed
presentation that serves as our [documentation][documentation].
This is the most up-to-date information, so please let us know if you see
things that need to be fixed.
# Basic Setup
## Dependencies
Please see the Dockerfile for the required versions of tools.
In general, the OpenRAM compiler has very few dependencies:
+ Docker
+ Make
+ Python 3.6 or higher
+ Various Python packages (pip install -r requirements.txt)
+ [Git]
## Docker
We have a [docker setup](./docker) to run OpenRAM. To use this, you should run:
```
cd OpenRAM/docker
make build
```
This must be run once and will take a while to build all the tools.
## Environment
You must set two environment variables:
+ OPENRAM\_HOME should point to the compiler source directory.
+ OPENERAM\_TECH should point to one or more root technology directories (colon separated).
You should also add OPENRAM\_HOME to your PYTHONPATH.
For example add this to your .bashrc:
```
export OPENRAM_HOME="$HOME/OpenRAM/compiler"
export OPENRAM_TECH="$HOME/OpenRAM/technology"
```
You should also add OPENRAM\_HOME to your PYTHONPATH:
```
export PYTHONPATH=$OPENRAM_HOME
```
Note that if you want symbols to resolve in your editor, you may also want to add the specific technology
directory that you use and any custom technology modules as well. For example:
```
export PYTHONPATH="$OPENRAM_HOME:$OPENRAM_TECH/sky130:$OPENRAM_TECH/sky130/custom"
```
We include the tech files necessary for [SCMOS] SCN4M_SUBM,
[FreePDK45]. The [SCMOS] spice models, however, are
generic and should be replaced with foundry models. You may get the
entire [FreePDK45 PDK here][FreePDK45].
### Sky130 Setup
To install [Sky130], you must have the open_pdks files installed in $PDK_ROOT.
To install this automatically, you can run:
```
cd $HOME/OpenRAM
make pdk
```
Then you must also install the [Sky130] SRAM build space and the appropriate cell views
by running:
```
cd $HOME/OpenRAM
make install
```
# Basic Usage
Once you have defined the environment, you can run OpenRAM from the command line
using a single configuration file written in Python.
For example, create a file called *myconfig.py* specifying the following
parameters for your memory:
```
# Data word size
word_size = 2
# Number of words in the memory
num_words = 16
# Technology to use in $OPENRAM_TECH
tech_name = "scn4m_subm"
# You can use the technology nominal corner only
nominal_corner_only = True
# Or you can specify particular corners
# Process corners to characterize
# process_corners = ["SS", "TT", "FF"]
# Voltage corners to characterize
# supply_voltages = [ 3.0, 3.3, 3.5 ]
# Temperature corners to characterize
# temperatures = [ 0, 25 100]
# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False
```
You can then run OpenRAM by executing:
```
python3 $OPENRAM_HOME/openram.py myconfig
```
You can see all of the options for the configuration file in
$OPENRAM\_HOME/options.py
To run designs in Docker, it is suggested to use, for example:
```
cd OpenRAM/macros
make example_config_scn4m_subm
```
# Unit Tests
Regression testing performs a number of tests for all modules in OpenRAM.
From the unit test directory ($OPENRAM\_HOME/tests),
use the following command to run all regression tests:
```
cd OpenRAM/compiler/tests
make -j 3
```
The -j can run with 3 threads. By default, this will run in all technologies.
To run a specific test in all technologies:
```
cd OpenRAM/compiler/tests
make 05_bitcell_array_test
```
To run a specific technology:
```
cd OpenRAM/compiler/tests
TECHS=scn4m_subm make 05_bitcell_array_test
```
To increase the verbosity of the test, add one (or more) -v options and
pass it as an argument to OpenRAM:
```
ARGS="-v" make 05_bitcell_array_test
```
Unit test results are put in a directory:
```
OpenRAM/compiler/tests/results/<technology>/<test>
```
If the test fails, there will be a tmp directory with intermediate results.
If the test passes, this directory will be deleted to save space.
You can view the .out file to see what the output of a test is in either case.
Please see our [documentation][documentation] and let us know if anything needs
updating.
# Get Involved
@ -194,17 +33,25 @@ You can view the .out file to see what the output of a test is in either case.
# Further Help
+ [Additional hints](./HINTS.md)
+ [Documentation][documentation]
+ [OpenRAM Slack Workspace][Slack]
+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
+ <a rel="me" href="https://fosstodon.org/@mrg">@mrg@fostodon.org</a>
# License
OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
# Publications
+ M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016
+ S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506.
+ E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017
+ B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization", IEEE International Symposium on Circuits and Systems (ISCAS), 2019
+ B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019
+ H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019
# Contributors & Acknowledgment
- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
@ -223,9 +70,9 @@ If I forgot to add you, please let me know!
[Github issues]: https://github.com/VLSIDA/OpenRAM/issues
[Github pull request]: https://github.com/VLSIDA/OpenRAM/pulls
[Github project]: https://github.com/VLSIDA/OpenRAM
[Github project]: https://github.com/VLSIDA/OpenRAM
[documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing
[documentation]: docs/source/index.md
[dev-group]: mailto:openram-dev-group@ucsc.edu
[user-group]: mailto:openram-user-group@ucsc.edu
[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu

31
__init__.py Normal file
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@ -0,0 +1,31 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
# Attempt to add the source code to the PYTHONPATH here before running globals.init_openram().
try:
OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
except:
OPENRAM_HOME = os.path.dirname(os.path.abspath(__file__)) + "/compiler"
if not os.path.isdir(OPENRAM_HOME):
assert False
# Make sure that OPENRAM_HOME is an environment variable just in case
if "OPENRAM_HOME" not in os.environ.keys():
os.environ["OPENRAM_HOME"] = OPENRAM_HOME
# Prepend $OPENRAM_HOME to __path__ so that openram will use those modules
__path__.insert(0, OPENRAM_HOME)
# Import everything in globals.py
from .globals import *
# Import classes in the "openram" namespace
# sram_config should be imported before sram
from .sram_config import *
from .sram import *

2
compiler/Makefile
View File

@ -95,7 +95,7 @@ model: $(STAMPS)
$(eval bname=$(basename $(notdir $@)))
$(eval config_path=$(CONFIG_DIR)/$(addsuffix .py, $(notdir $(basename $@))))
mkdir -p $(SIM_DIR)/$(bname)
-python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $(config_path) 2>&1 > /dev/null
-python3 $(OPENRAM_HOME)/../sram_compiler.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $(config_path) 2>&1 > /dev/null
touch $@
clean_model:

5
compiler/base/__init__.py
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@ -1,3 +1,8 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .channel_route import *
from .contact import *
from .delay_data import *

7
compiler/base/channel_route.py
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@ -1,13 +1,13 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import collections
import debug
from tech import drc
from openram import debug
from openram.tech import drc
from .vector import vector
from .design import design
@ -405,4 +405,3 @@ class channel_route(design):
to_layer=self.horizontal_layer,
offset=pin_pos)

8
compiler/base/contact.py
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@ -1,15 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from openram import debug
from openram.tech import drc, layer, preferred_directions
from openram.tech import layer as tech_layers
from .hierarchy_design import hierarchy_design
from .vector import vector
from tech import drc, layer, preferred_directions
from tech import layer as tech_layers
class contact(hierarchy_design):

7
compiler/base/delay_data.py
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@ -1,12 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
class delay_data():
"""
This is the delay class to represent the delay information
@ -38,7 +37,3 @@ class delay_data():
assert isinstance(other, delay_data)
return delay_data(other.delay + self.delay,
self.slew)

14
compiler/base/design.py
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@ -1,15 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from tech import GDS, layer
from tech import preferred_directions
from tech import cell_properties as props
from globals import OPTS
from openram import debug
from openram.tech import GDS, layer
from openram.tech import preferred_directions
from openram.tech import cell_properties as props
from openram import OPTS
from . import utils
from .hierarchy_design import hierarchy_design
@ -67,7 +67,7 @@ class design(hierarchy_design):
self.setup_multiport_constants()
try:
from tech import power_grid
from openram.tech import power_grid
self.supply_stack = power_grid
except ImportError:
# if no power_grid is specified by tech we use sensible defaults

6
compiler/base/errors.py
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@ -1,4 +1,8 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
class drc_error(Exception):
"""Exception raised for DRC errors.

12
compiler/base/geometry.py
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@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
@ -8,14 +8,14 @@
"""
This provides a set of useful generic types for the gdsMill interface.
"""
import debug
from .vector import vector
import tech
import math
import copy
import numpy as np
from globals import OPTS
from openram import debug
from openram import tech
from openram import OPTS
from .utils import round_to_grid
from .vector import vector
class geometry:
@ -249,7 +249,6 @@ class instance(geometry):
""" Return an absolute pin that is offset and transformed based on
this instance location. Index will return one of several pins."""
import copy
if index == -1:
pin = copy.deepcopy(self.mod.get_pin(name))
pin.transform(self.offset, self.mirror, self.rotate)
@ -267,7 +266,6 @@ class instance(geometry):
""" Return an absolute pin that is offset and transformed based on
this instance location. """
import copy
pin = copy.deepcopy(self.mod.get_pins(name))
new_pins = []

14
compiler/base/hierarchy_design.py
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@ -1,15 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
from openram import debug
from openram import OPTS
from .hierarchy_layout import layout
from .hierarchy_spice import spice
import debug
import os
from globals import OPTS
class hierarchy_design(spice, layout):
@ -49,7 +49,7 @@ class hierarchy_design(spice, layout):
def DRC_LVS(self, final_verification=False, force_check=False):
"""Checks both DRC and LVS for a module"""
import verify
from openram import verify
# No layout to check
if OPTS.netlist_only:
@ -82,7 +82,7 @@ class hierarchy_design(spice, layout):
def DRC(self, final_verification=False):
"""Checks DRC for a module"""
import verify
from openram import verify
# Unit tests will check themselves.
# Do not run if disabled in options.
@ -102,7 +102,7 @@ class hierarchy_design(spice, layout):
def LVS(self, final_verification=False):
"""Checks LVS for a module"""
import verify
from openram import verify
# Unit tests will check themselves.
# Do not run if disabled in options.

42
compiler/base/hierarchy_layout.py
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@ -1,32 +1,32 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
import sys
import os
import re
from math import sqrt
import debug
from gdsMill import gdsMill
import tech
from tech import drc, GDS
from tech import layer as tech_layer
from tech import layer_indices as tech_layer_indices
from tech import preferred_directions
from tech import layer_stacks as tech_layer_stacks
from tech import active_stack as tech_active_stack
from sram_factory import factory
from globals import OPTS
from openram import debug
from openram.gdsMill import gdsMill
from openram import tech
from openram.tech import drc, GDS
from openram.tech import layer as tech_layer
from openram.tech import layer_indices as tech_layer_indices
from openram.tech import preferred_directions
from openram.tech import layer_stacks as tech_layer_stacks
from openram.tech import active_stack as tech_active_stack
from openram.sram_factory import factory
from openram import OPTS
from .vector import vector
from .pin_layout import pin_layout
from .utils import round_to_grid
from . import geometry
try:
from tech import special_purposes
from openram.tech import special_purposes
except ImportError:
special_purposes = {}
@ -171,7 +171,7 @@ class layout():
in many places in the compiler.
"""
try:
from tech import power_grid
from openram.tech import power_grid
layout.pwr_grid_layers = [power_grid[0], power_grid[2]]
except ImportError:
layout.pwr_grid_layers = ["m3", "m4"]
@ -1253,7 +1253,6 @@ class layout():
def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
""" Add a three layer via structure. """
from sram_factory import factory
via = factory.create(module_type="contact",
layer_stack=layers,
dimensions=size,
@ -1272,7 +1271,6 @@ class layout():
Add a three layer via structure by the center coordinate
accounting for mirroring and rotation.
"""
from sram_factory import factory
via = factory.create(module_type="contact",
layer_stack=layers,
dimensions=size,
@ -1379,10 +1377,10 @@ class layout():
def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
"""Adds a ptx module to the design."""
import ptx
mos = ptx.ptx(width=width,
mults=mults,
tx_type=tx_type)
from openram.modules import ptx
mos = ptx(width=width,
mults=mults,
tx_type=tx_type)
inst = self.add_inst(name=mos.name,
mod=mos,
offset=offset,
@ -2176,7 +2174,6 @@ class layout():
# Find the number of vias for this pitch
supply_vias = 1
from sram_factory import factory
while True:
c = factory.create(module_type="contact",
layer_stack=self.m1_stack,
@ -2289,7 +2286,6 @@ class layout():
# Find the number of vias for this pitch
self.supply_vias = 1
from sram_factory import factory
while True:
c = factory.create(module_type="contact",
layer_stack=self.m1_stack,

46
compiler/base/hierarchy_spice.py
View File

@ -1,17 +1,18 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
import re
import os
import re
import math
import tech
from globals import OPTS
import textwrap as tr
from pprint import pformat
from openram import debug
from openram import tech
from openram import OPTS
from .delay_data import delay_data
from .wire_spice_model import wire_spice_model
from .power_data import power_data
@ -37,7 +38,7 @@ class spice():
# If we have a separate lvs directory, then all the lvs files
# should be in there (all or nothing!)
try:
from tech import lvs_name
from openram.tech import lvs_name
lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
except ImportError:
lvs_dir = OPTS.openram_tech + "lvs_lib/"
@ -338,19 +339,21 @@ class spice():
return
# write out the first spice line (the subcircuit)
sp.write("\n.SUBCKT {0} {1}\n".format(self.cell_name,
" ".join(self.pins)))
wrapped_pins = "\n+ ".join(tr.wrap(" ".join(self.pins)))
sp.write("\n.SUBCKT {0}\n+ {1}\n".format(self.cell_name,
wrapped_pins))
# write a PININFO line
pin_info = "*.PININFO"
for pin in self.pins:
if self.pin_type[pin] == "INPUT":
pin_info += " {0}:I".format(pin)
elif self.pin_type[pin] == "OUTPUT":
pin_info += " {0}:O".format(pin)
else:
pin_info += " {0}:B".format(pin)
sp.write(pin_info + "\n")
if False:
pin_info = "*.PININFO"
for pin in self.pins:
if self.pin_type[pin] == "INPUT":
pin_info += " {0}:I".format(pin)
elif self.pin_type[pin] == "OUTPUT":
pin_info += " {0}:O".format(pin)
else:
pin_info += " {0}:B".format(pin)
sp.write(pin_info + "\n")
# Also write pins as comments
for pin in self.pins:
@ -391,9 +394,11 @@ class spice():
" ".join(self.conns[i])))
sp.write("\n")
else:
sp.write("X{0} {1} {2}\n".format(self.insts[i].name,
" ".join(self.conns[i]),
self.insts[i].mod.cell_name))
wrapped_connections = "\n+ ".join(tr.wrap(" ".join(self.conns[i])))
sp.write("X{0}\n+ {1}\n+ {2}\n".format(self.insts[i].name,
wrapped_connections,
self.insts[i].mod.cell_name))
sp.write(".ENDS {0}\n".format(self.cell_name))
@ -409,6 +414,7 @@ class spice():
sp.write("\n")
def sp_write(self, spname, lvs=False, trim=False):
"""Writes the spice to files"""
debug.info(3, "Writing to {0}".format(spname))

14
compiler/base/lef.py
View File

@ -1,17 +1,17 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from base import vector
from base import pin_layout
from tech import layer_names
import os
import shutil
from globals import OPTS
from openram import debug
from openram.base import vector
from openram.base import pin_layout
from openram.tech import layer_names
from openram import OPTS
class lef:
@ -64,7 +64,7 @@ class lef:
f.write('puts "Finished writing LEF cell {}"\n'.format(self.name))
f.close()
os.system("chmod u+x {}".format(run_file))
from run_script import run_script
from openram.verify.run_script import run_script
(outfile, errfile, resultsfile) = run_script(self.name, "lef")
def lef_write(self, lef_name):

7
compiler/base/logical_effort.py
View File

@ -1,12 +1,13 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from tech import parameter
from openram import debug
from openram.tech import parameter
class logical_effort():
"""

20
compiler/base/pin_layout.py
View File

@ -1,15 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from tech import GDS, drc
from .vector import vector
from tech import layer, layer_indices
import math
from openram import debug
from openram.tech import GDS, drc
from openram.tech import layer, layer_indices
from .vector import vector
class pin_layout:
@ -48,8 +48,8 @@ class pin_layout:
else:
try:
from tech import layer_override
from tech import layer_override_name
from openram.tech import layer_override
from openram.tech import layer_override_name
if layer_override[name]:
self.lpp = layer_override[name]
self.layer = "pwellp"
@ -406,15 +406,15 @@ class pin_layout:
# Try to use a global pin purpose if it exists,
# otherwise, use the regular purpose
try:
from tech import pin_purpose as global_pin_purpose
from openram.tech import pin_purpose as global_pin_purpose
pin_purpose = global_pin_purpose
except ImportError:
pass
try:
from tech import label_purpose
from openram.tech import label_purpose
try:
from tech import layer_override_purpose
from openram.tech import layer_override_purpose
if pin_layer_num in layer_override_purpose:
layer_num = layer_override_purpose[pin_layer_num][0]
label_purpose = layer_override_purpose[pin_layer_num][1]

2
compiler/base/power_data.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.

11
compiler/base/route.py
View File

@ -1,17 +1,18 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from itertools import tee
from openram import debug
from openram.sram_factory import factory
from openram.tech import drc
from .design import design
from .vector import vector
from .vector3d import vector3d
from tech import drc
from itertools import tee
from sram_factory import factory
class route(design):
"""

7
compiler/base/timing_graph.py
View File

@ -1,6 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import copy
from collections import defaultdict
import debug
from openram import debug
class timing_graph():

18
compiler/base/utils.py
View File

@ -1,24 +1,22 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
import math
from gdsMill import gdsMill
import tech
import globals
import debug
from openram import debug
from openram import tech
from openram.gdsMill import gdsMill
from openram import OPTS
from .vector import vector
from .pin_layout import pin_layout
try:
from tech import special_purposes
from openram.tech import special_purposes
except ImportError:
special_purposes = {}
OPTS = globals.OPTS
def ceil(decimal):
@ -159,7 +157,7 @@ def get_gds_pins(pin_names, name, gds_filename, units):
# may have must-connect pins
if isinstance(lpp[1], list):
try:
from tech import layer_override
from openram.tech import layer_override
if layer_override[pin_name]:
lpp = layer_override[pin_name.textString]
except:

5
compiler/base/vector.py
View File

@ -1,13 +1,12 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import math
import tech
from openram import tech
class vector():

2
compiler/base/vector3d.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.

4
compiler/base/verilog.py
View File

@ -1,12 +1,12 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import math
from tech import spice
from openram.tech import spice
class verilog:

8
compiler/base/wire.py
View File

@ -1,13 +1,13 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from tech import drc
from openram.tech import drc
from openram.sram_factory import factory
from .wire_path import wire_path
from sram_factory import factory
class wire(wire_path):
@ -71,7 +71,7 @@ class wire(wire_path):
# This is here for the unit tests which may not have
# initialized the static parts of the layout class yet.
from base import layout
from openram.base import layout
layout("fake", "fake")
(layer1, via, layer2) = layer_stack

11
compiler/base/wire_path.py
View File

@ -1,15 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from .vector import vector
from .utils import snap_to_grid
from openram.tech import drc
from openram.tech import layer as techlayer
from .design import design
from tech import drc
from tech import layer as techlayer
from .utils import snap_to_grid
from .vector import vector
def create_rectilinear_route(my_list):
""" Add intermediate nodes if it isn't rectilinear. Also skip

6
compiler/base/wire_spice_model.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
@ -16,14 +16,14 @@ class wire_spice_model():
self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
def cal_wire_c(self, wire_length, wire_width):
from tech import spice
from openram.tech import spice
# Convert the F/um^2 to fF/um^2 then multiple by width and length
total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
wire_c = total_c / self.lump_num
return wire_c
def cal_wire_r(self, wire_length, wire_width):
from tech import spice
from openram.tech import spice
total_r = spice["wire_unit_r"] * wire_length / wire_width
wire_r = total_r / self.lump_num
return wire_r

7
compiler/characterizer/__init__.py
View File

@ -1,13 +1,13 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
import debug
from globals import OPTS, find_exe, get_tool
from openram import debug
from openram import OPTS, find_exe, get_tool
from .lib import *
from .delay import *
from .elmore import *
@ -56,4 +56,3 @@ if not OPTS.analytical_delay:
else:
debug.info(1, "Analytical model enabled.")

10
compiler/characterizer/analytical_util.py
View File

@ -1,16 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
import os
import csv
import math
import numpy as np
import os
from openram import debug
process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0}

2
compiler/characterizer/bit_polarity.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.

13
compiler/characterizer/cacti.py
View File

@ -1,17 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from .simulation import simulation
from globals import OPTS
import debug
import tech
import math
from openram import debug
from openram import tech
from openram import OPTS
from .simulation import simulation
class cacti(simulation):
"""

6
compiler/characterizer/charutils.py
View File

@ -1,14 +1,14 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
import re
import debug
from globals import OPTS
from openram import debug
from openram import OPTS
def relative_compare(value1, value2, error_tolerance=0.001):

10
compiler/characterizer/delay.py
View File

@ -1,20 +1,20 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import shutil
import debug
import tech
import math
import shutil
from openram import debug
from openram import tech
from openram import OPTS
from .stimuli import *
from .trim_spice import *
from .charutils import *
from .sram_op import *
from .bit_polarity import *
from globals import OPTS
from .simulation import simulation
from .measurements import *

8
compiler/characterizer/elmore.py
View File

@ -1,14 +1,14 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from openram import debug
from openram import OPTS
from .simulation import simulation
from globals import OPTS
import debug
class elmore(simulation):
"""

10
compiler/characterizer/functional.py
View File

@ -1,18 +1,18 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import collections
import debug
import random
import math
import random
import collections
from numpy import binary_repr
from openram import debug
from openram import OPTS
from .stimuli import *
from .charutils import *
from globals import OPTS
from .simulation import simulation

14
compiler/characterizer/lib.py
View File

@ -1,21 +1,21 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os,sys,re
import os, sys, re
import time
import debug
import datetime
import numpy as np
from openram import debug
from openram import tech
from openram.tech import spice
from openram import OPTS
from .setup_hold import *
from .delay import *
from .charutils import *
import tech
import numpy as np
from globals import OPTS
from tech import spice
class lib:

10
compiler/characterizer/linear_regression.py
View File

@ -1,17 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from .regression_model import regression_model
from sklearn.linear_model import Ridge
from globals import OPTS
import debug
from sklearn.linear_model import LinearRegression
from openram import debug
from openram import OPTS
from .regression_model import regression_model
class linear_regression(regression_model):

7
compiler/characterizer/measurements.py
View File

@ -1,16 +1,17 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from tech import drc, parameter, spice
from abc import ABC, abstractmethod
from openram import debug
from openram.tech import drc, parameter, spice
from .stimuli import *
from .charutils import *
class spice_measurement(ABC):
"""Base class for spice stimulus measurements."""
def __init__(self, measure_name, measure_scale=None, has_port=True):

8
compiler/characterizer/model_check.py
View File

@ -1,16 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
import tech
from openram import debug
from openram import tech
from openram import OPTS
from .stimuli import *
from .trim_spice import *
from .charutils import *
from globals import OPTS
from .delay import delay
from .measurements import *

9
compiler/characterizer/neural_network.py
View File

@ -1,15 +1,14 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from .regression_model import regression_model
from globals import OPTS
import debug
from sklearn.neural_network import MLPRegressor
from openram import debug
from openram import OPTS
from .regression_model import regression_model
class neural_network(regression_model):

9
compiler/characterizer/regression_model.py
View File

@ -1,17 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import math
from openram import debug
from openram import OPTS
from .analytical_util import *
from .simulation import simulation
from globals import OPTS
import debug
import math
relative_data_path = "sim_data"
data_file = "sim_data.csv"

10
compiler/characterizer/setup_hold.py
View File

@ -1,16 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import tech
from openram import debug
from openram.sram_factory import factory
from openram import tech
from openram import OPTS
from .stimuli import *
import debug
from .charutils import *
from globals import OPTS
from sram_factory import factory
class setup_hold():

12
compiler/characterizer/simulation.py
View File

@ -1,16 +1,16 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
import math
import tech
from globals import OPTS
from sram_factory import factory
from base import timing_graph
from openram import debug
from openram.base import timing_graph
from openram.sram_factory import factory
from openram import tech
from openram import OPTS
class simulation():

2
compiler/characterizer/sram_op.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.

10
compiler/characterizer/stimuli.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
@ -11,12 +11,12 @@ various functions that can be be used to generate stimulus for other
simulations as well.
"""
import tech
import debug
import subprocess
import os
import subprocess
import numpy as np
from globals import OPTS
from openram import debug
from openram import tech
from openram import OPTS
class stimuli():

6
compiler/characterizer/trim_spice.py
View File

@ -1,13 +1,13 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from math import log,ceil
import re
from math import log, ceil
from openram import debug
class trim_spice():

5
compiler/datasheet/__init__.py
View File

@ -1 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .datasheet_gen import datasheet_gen

9
compiler/datasheet/add_db.py
View File

@ -1,14 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from pathlib import Path
import glob
import os
import sys
import os
import glob
from pathlib import Path
# This is the path to the directory you would like to search
# This directory is searched recursively for .html files

6
compiler/datasheet/datasheet.py
View File

@ -1,14 +1,14 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from .table_gen import *
import os
import base64
from globals import OPTS
from openram import OPTS
from .table_gen import *
class datasheet():

4
compiler/datasheet/datasheet_gen.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
@ -15,10 +15,10 @@ a web friendly html datasheet.
# Improve css
from globals import OPTS
import os
import math
import csv
from openram import OPTS
from .datasheet import datasheet
from .table_gen import table_gen

3
compiler/datasheet/table_gen.py
View File

@ -1,12 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
class table_gen:
"""small library of functions to generate the html tables"""

14
compiler/debug.py
View File

@ -1,15 +1,15 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import os
import inspect
import globals
import sys
import os
import pdb
import inspect
from openram import globals
# the debug levels:
# 0 = minimum output (default)
@ -96,7 +96,7 @@ log.create_file = True
def info(lev, str):
from globals import OPTS
from openram.globals import OPTS
# 99 is a special never print level
if lev == 99:
return
@ -114,7 +114,7 @@ def info(lev, str):
def archive():
from globals import OPTS
from openram.globals import OPTS
try:
OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
except:
@ -131,7 +131,7 @@ def bp():
An empty function so you can set soft breakpoints in pdb.
Usage:
1) Add a breakpoint anywhere in your code with "import debug; debug.bp()".
2) Run "python3 -m pdb openram.py config.py" or "python3 -m pdb 05_bitcell_array.test" (for example)
2) Run "python3 -m pdb sram_compiler.py config.py" or "python3 -m pdb 05_bitcell_array.test" (for example)
3) When pdb starts, run "break debug.bp" to set a SOFT breakpoint. (Or you can add this to your ~/.pdbrc)
4) Then run "cont" to continue.
5) You can now set additional breakpoints or display commands

5
compiler/drc/__init__.py
View File

@ -1,3 +1,8 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .custom_cell_properties import *
from .custom_layer_properties import *
from .design_rules import *

11
compiler/drc/custom_cell_properties.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2020 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
@ -186,12 +186,15 @@ class cell_properties():
self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw"
self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw"
self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw"
self.names["internal"] = "internal"
self.use_strap = False
self._ptx = _ptx(model_is_subckt=False,
bin_spice_models=False)
self._pgate = _pgate(add_implants=False)
self._inv_dec = cell(["A", "Z", "vdd", "gnd"],
["INPUT", "OUTPUT", "POWER", "GROUND"])
@ -231,6 +234,12 @@ class cell_properties():
self._row_cap_2port = bitcell(["wl0", "wl1", "gnd"],
["INPUT", "INPUT", "POWER", "GROUND"])
self._internal = cell([],[])
@property
def internal(self):
return self._internal
@property
def ptx(self):
return self._ptx

3
compiler/drc/custom_layer_properties.py
View File

@ -1,12 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2020 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
class _bank:
def __init__(self, stack, pitch):
# bank

4
compiler/drc/design_rules.py
View File

@ -1,11 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from openram import debug
from .drc_value import *
from .drc_lut import *

4
compiler/drc/drc_lut.py
View File

@ -1,11 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import debug
from openram import debug
class drc_lut():

3
compiler/drc/drc_value.py
View File

@ -1,12 +1,11 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
class drc_value():
"""
A single DRC value.

2
compiler/drc/module_type.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.

6
compiler/gdsMill/gdsMill/pdfLayout.py
View File

@ -1,8 +1,8 @@
import pyx
import math
from numpy import matrix
from gdsPrimitives import *
import random
from numpy import matrix
from openram.gdsMill import pyx
from .gdsPrimitives import *
class pdfLayout:
"""Class representing a view for a layout as a PDF"""

8
compiler/gdsMill/gdsMill/vlsiLayout.py
View File

@ -1,8 +1,8 @@
from .gdsPrimitives import *
import math
from datetime import *
import numpy as np
import math
import debug
from openram import debug
from .gdsPrimitives import *
class VlsiLayout:
@ -774,7 +774,7 @@ class VlsiLayout:
else:
label_text = label.textString
try:
from tech import layer_override
from openram.tech import layer_override
if layer_override[label_text]:
shapes = self.getAllShapes((layer_override[label_text][0], None))
if not shapes:

2
compiler/gen_stimulus.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.

86
compiler/globals.py
View File

@ -1,6 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2022 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
@ -9,22 +9,22 @@
This is called globals.py, but it actually parses all the arguments
and performs the global OpenRAM setup as well.
"""
import sys
import os
import debug
import re
import shutil
import optparse
import options
import sys
import re
import copy
import importlib
import getpass
import subprocess
from openram import debug
from openram import options
VERSION = "1.2.0"
NAME = "OpenRAM v{}".format(VERSION)
USAGE = "openram.py [options] <config file>\nUse -h for help.\n"
USAGE = "sram_compiler.py [options] <config file>\nUse -h for help.\n"
OPTS = options.options()
CHECKPOINT_OPTS = None
@ -141,9 +141,6 @@ def print_banner():
debug.print_raw("|=========" + user_info.center(60) + "=========|")
dev_info = "Development help: openram-dev-group@ucsc.edu"
debug.print_raw("|=========" + dev_info.center(60) + "=========|")
if OPTS.openram_temp:
temp_info = "Temp dir: {}".format(OPTS.openram_temp)
debug.print_raw("|=========" + temp_info.center(60) + "=========|")
debug.print_raw("|=========" + "See LICENSE for license info".center(60) + "=========|")
debug.print_raw("|==============================================================================|")
@ -188,7 +185,7 @@ def check_versions():
OPTS.coverage = 0
def init_openram(config_file, is_unit_test=True):
def init_openram(config_file, is_unit_test=False):
""" Initialize the technology, paths, simulators, etc. """
check_versions()
@ -205,7 +202,7 @@ def init_openram(config_file, is_unit_test=True):
init_paths()
from sram_factory import factory
from openram.sram_factory import factory
factory.reset()
global OPTS
@ -225,8 +222,8 @@ def init_openram(config_file, is_unit_test=True):
setup_bitcell()
# Import these to find the executables for checkpointing
import characterizer
import verify
from openram import characterizer
from openram import verify
# Make a checkpoint of the options so we can restore
# after each unit test
if not CHECKPOINT_OPTS:
@ -252,7 +249,7 @@ def setup_bitcell():
# See if bitcell exists
try:
c = importlib.import_module("modules." + OPTS.bitcell)
c = importlib.import_module("openram.modules." + OPTS.bitcell)
mod = getattr(c, OPTS.bitcell)
except ImportError:
# Use the pbitcell if we couldn't find a custom bitcell
@ -297,7 +294,7 @@ def get_tool(tool_type, preferences, default_name=None):
return(None, "")
def read_config(config_file, is_unit_test=True):
def read_config(config_file, is_unit_test=False):
"""
Read the configuration file that defines a few parameters. The
config file is just a Python file that defines some config
@ -388,7 +385,7 @@ def end_openram():
cleanup_paths()
if OPTS.check_lvsdrc:
import verify
from openram import verify
verify.print_drc_stats()
verify.print_lvs_stats()
verify.print_pex_stats()
@ -432,16 +429,8 @@ def setup_paths():
global OPTS
try:
OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
except:
debug.error("$OPENRAM_HOME is not properly defined.", 1)
debug.check(os.path.isdir(OPENRAM_HOME),
"$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME))
if OPENRAM_HOME not in sys.path:
debug.error("Please add OPENRAM_HOME to the PYTHONPATH.", -1)
from openram import OPENRAM_HOME
debug.info(1, "OpenRAM source code found in {}".format(OPENRAM_HOME))
# Use a unique temp subdirectory if multithreaded
if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp":
@ -511,7 +500,7 @@ def init_paths():
def set_default_corner():
""" Set the default corner. """
import tech
from openram import tech
# Set some default options now based on the technology...
if (OPTS.process_corners == ""):
if OPTS.nominal_corner_only:
@ -544,14 +533,32 @@ def import_tech():
""" Dynamically adds the tech directory to the path and imports it. """
global OPTS
debug.info(2,
"Importing technology: " + OPTS.tech_name)
debug.info(2, "Importing technology: " + OPTS.tech_name)
# environment variable should point to the technology dir
OPENRAM_TECH = ""
# Check if $OPENRAM_TECH is defined
try:
OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH"))
except:
debug.error("$OPENRAM_TECH environment variable is not defined.", 1)
debug.info(2,
"$OPENRAM_TECH environment variable is not defined. "
"Only the default technology modules will be considered if installed.")
# Point to the default technology modules that are part of the openram package
try:
import openram
if OPENRAM_TECH != "":
OPENRAM_TECH += ":"
OPENRAM_TECH += os.path.dirname(openram.__file__) + "/technology"
except:
if OPENRAM_TECH == "":
debug.warning("Couldn't find a tech directory. "
"Install openram library or set $OPENRAM_TECH.")
debug.info(1, "Tech directory found in {}".format(OPENRAM_TECH))
# Add this environment variable to os.environ
os.environ["OPENRAM_TECH"] = OPENRAM_TECH
# Add all of the paths
for tech_path in OPENRAM_TECH.split(":"):
@ -568,18 +575,23 @@ def import_tech():
OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
# Prepend the tech directory so it is sourced FIRST
# Append tech_path to openram.__path__ to import it from openram
tech_path = OPTS.openram_tech
sys.path.insert(0, tech_path)
openram.__path__.append(tech_path)
try:
import tech
from openram import tech
except ImportError:
debug.error("Could not load tech module.", -1)
# Prepend custom modules of the technology to the path, if they exist
custom_mod_path = os.path.join(tech_path, "modules/")
# Remove OPENRAM_TECH from sys.path because we should be done with those
for tech_path in OPENRAM_TECH.split(":"):
sys.path.remove(tech_path)
# Add the custom modules to "tech"
custom_mod_path = os.path.join(tech_path, "custom/")
if os.path.exists(custom_mod_path):
sys.path.insert(0, custom_mod_path)
from openram import tech
tech.__path__.append(custom_mod_path)
def print_time(name, now_time, last_time=None, indentation=2):

5
compiler/model_configs/shared_config.py
View File

@ -1 +1,6 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
model_name = "cacti"

7
compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 10
num_words = 64
words_per_row = 4

9
compiler/model_configs/sram_128b_1024_1rw.py
View File

@ -1,8 +1,13 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 128
num_words = 1024
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

7
compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 12
num_words = 128
words_per_row = 4

7
compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 12
num_words = 16
words_per_row = 1

7
compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 12
num_words = 256
words_per_row = 16

7
compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 12
num_words = 256
words_per_row = 8

7
compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 14
num_words = 32
words_per_row = 2

7
compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 15
num_words = 512
words_per_row = 8

7
compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 16
num_words = 1024
words_per_row = 16

7
compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 17
num_words = 1024
words_per_row = 16

7
compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 17
num_words = 256
words_per_row = 16

7
compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 18
num_words = 128
words_per_row = 2

7
compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 18
num_words = 32
words_per_row = 1

7
compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 21
num_words = 1024
words_per_row = 4

7
compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 22
num_words = 512
words_per_row = 16

7
compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 23
num_words = 1024
words_per_row = 16

7
compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 26
num_words = 64
words_per_row = 4

7
compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 27
num_words = 1024
words_per_row = 4

7
compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 27
num_words = 256
words_per_row = 8

7
compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py
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@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 27
num_words = 512
words_per_row = 4

7
compiler/model_configs/sram_32b_1024_1rw.py
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@ -1,3 +1,8 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from shared_config import *
word_size = 32
num_words = 1024
@ -5,4 +10,4 @@ num_words = 1024
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

9
compiler/model_configs/sram_32b_2048_1rw.py
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@ -1,8 +1,13 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 32
num_words = 2048
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

9
compiler/model_configs/sram_32b_256_1rw.py
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@ -1,8 +1,13 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 32
num_words = 256
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

7
compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py
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@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 32
num_words = 32
words_per_row = 1

9
compiler/model_configs/sram_32b_512_1rw.py
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@ -1,8 +1,13 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 32
num_words = 512
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

7
compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 4
num_words = 16
words_per_row = 1

7
compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 4
num_words = 32
words_per_row = 2

7
compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 4
num_words = 64
words_per_row = 4

7
compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py
View File

@ -1,4 +1,9 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 5
num_words = 256
words_per_row = 16

9
compiler/model_configs/sram_64b_1024_1rw.py
View File

@ -1,8 +1,13 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 64
num_words = 1024
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

9
compiler/model_configs/sram_64b_512_1rw.py
View File

@ -1,8 +1,13 @@
from shared_config import *
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved.
#
from .shared_config import *
word_size = 64
num_words = 512
output_extended_config = True
output_datasheet_info = True
netlist_only = True
nominal_corner_only = True
nominal_corner_only = True

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