fix

2022-07-28 17:00:16 -07:00 · 2022-07-28 17:00:16 -07:00 · 7fe0f647ef
parent 8f955207d3
commit 7fe0f647ef
1 changed files with 1 additions and 1 deletions
--- a/compiler/modules/sram.py
+++ b/compiler/modules/sram.py
@ -42,7 +42,7 @@ class sram():

        if self.num_banks != 1:
            from sram_multibank import sram_multibank
-            mb = sram_multibank(s)
+            mb = sram_multibank(self.s)
            mb.verilog_write()

        self.s.create_netlist()