mirror of https://github.com/VLSIDA/OpenRAM.git
Template module done
This commit is contained in:
Bugra Onal
parent
0970095415
commit
2b1d0bd9f7
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@ -10,18 +10,18 @@ module multibank # (
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din,
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csb,
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web,
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dout,
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dout
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#>RW_PORTS
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#<R_PORTS
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clk,
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addr,
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csb,
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web,
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dout,
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dout
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#>R_PORTS
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);
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parameter RAM_DEPTH = 1 << ADRR_WIDTH;
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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parameter BANK_SEL = (NUM_BANKS <= 2)? 1 :
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(NUM_BANKS <= 4)? 2 :
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(NUM_BANKS <= 8)? 3 :
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@ -32,34 +32,42 @@ module multibank # (
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input [DATA_WIDTH - 1: 0] din;
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input csb;
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input web;
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output reg [DATA_WIDTH - 1 : 0] data;
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output reg [DATA_WIDTH - 1 : 0] dout;
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#!PORT_NUM!0#
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#<BANK_DEFS
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reg csb#$PORT_NUM$#;
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reg web#$PORT_NUM$#;
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reg dout#$PORT_NUM$#;
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reg [DATA_WIDTH - 1 : 0] dout#$PORT_NUM$#;
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#!PORT_NUM!PORT_NUM+1#
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#>BANK_DEFS
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#!PORT_NUM!0#
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#<BANK_INIT
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bank bank#$BANK_NUM$# #(DATA_WIDTH, ADDR_WIDTH) (
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bank #(DATA_WIDTH, ADDR_WIDTH) bank#$PORT_NUM$# (
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#<BANK_RW_PORTS
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.clk(clk),
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.addr(addr),
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.addr(addr[ADDR_WIDTH - BANK_SEL - 1 : 0]),
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.din(din),
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.csb(csb#$PORT_NUM$#),
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.web(web#$PORT_NUM$#),
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.dout(dout#$PORT_NUM$#),
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.dout(dout#$PORT_NUM$#)
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#!PORT_NUM!PORT_NUM+1#
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#>BANK_RW_PORTS
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)
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);
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#>BANK_INIT
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always @(posedge clk) begin
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case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
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#!PORT_NUM!0#
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#<BANK_CASE
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#$PORT_NUM$#: begin
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dout <= dout#$PORT_NUM$#;
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web#$PORT_NUM$# <= web;
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end
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#!PORT_NUM!PORT_NUM+1#
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#>BANK_CASE
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endcase
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end
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endmodule
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@ -1,47 +0,0 @@
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class TextSection:
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def __init__(self, name, parent):
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self.name = name
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self.parent = parent
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self.lines = []
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self.sections = []
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self.sectionPos = []
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self.lineNum = 0
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self.repeat = 0
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def addLine(self, line):
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self.lines.append(line)
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self.lineNum+= 1
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def addSection(self, section):
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self.sections.append(section)
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self.sectionPos.append(self.lineNum)
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def expand(self):
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for i
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class VerilogTemplate:
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def __init__(self, template, output);
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self.template = template
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self.output = output
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self.sections = []
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def readTemplate(self):
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lines = []
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with open(self.template, 'r') as f:
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lines = f.readlines()
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currentSection = TextSection('base', None)
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for line in lines:
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if line[:2] == '#<':
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section = TextSection(line[2:], currentSection)
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currentSection.addSection(section)
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currentSection = section
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if line[:2] == '#>' and line[2:] == section.name:
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currentSection = currentSection.parent
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else:
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currentSection.addLine(line)
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@ -0,0 +1,13 @@
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from verilog_template import verilog_template
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t = verilog_template('../sram/multibank_template.v')
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t.readTemplate()
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t.setSectionRepeat('RW_PORTS', 1)
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t.setSectionRepeat('R_PORTS', 0)
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t.setSectionRepeat('BANK_DEFS', 2)
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t.setSectionRepeat('BANK_INIT', 2)
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t.setSectionRepeat('BANK_CASE', 2)
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t.setTextDict('PORT_NUM', 0)
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t.generate('test.v')
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@ -0,0 +1,65 @@
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module multibank # (
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DATA_WIDTH = 32,
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ADDR_WIDTH= 8,
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NUM_BANKS=2
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)(
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clk,
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addr,
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din,
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csb,
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web,
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dout
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);
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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parameter BANK_SEL = (NUM_BANKS <= 2)? 1 :
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(NUM_BANKS <= 4)? 2 :
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(NUM_BANKS <= 8)? 3 :
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(NUM_BANKS <= 16)? 4 : 5;
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input clk;
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input [ADDR_WIDTH -1 : 0] addr;
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input [DATA_WIDTH - 1: 0] din;
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input csb;
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input web;
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output reg [DATA_WIDTH - 1 : 0] dout;
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reg csb0;
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reg web0;
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reg [DATA_WIDTH - 1 : 0] dout0;
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reg csb1;
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reg web1;
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reg [DATA_WIDTH - 1 : 0] dout1;
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bank #(DATA_WIDTH, ADDR_WIDTH) bank0 (
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.clk(clk),
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.addr(addr[ADDR_WIDTH - BANK_SEL - 1 : 0]),
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.din(din),
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.csb(csb0),
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.web(web0),
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.dout(dout0)
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);
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bank #(DATA_WIDTH, ADDR_WIDTH) bank1 (
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.clk(clk),
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.addr(addr[ADDR_WIDTH - BANK_SEL - 1 : 0]),
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.din(din),
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.csb(csb1),
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.web(web1),
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.dout(dout1)
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);
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always @(posedge clk) begin
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case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
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0: begin
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dout <= dout0;
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web0 <= web;
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end
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1: begin
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dout <= dout1;
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web1 <= web;
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end
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endcase
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end
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endmodule
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@ -0,0 +1,103 @@
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class text_section:
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def __init__(self, name, parent):
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self.name = name
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self.parent = parent
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self.lines = []
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self.sections = []
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self.sectionPos = []
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self.lineNum = 0
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self.repeat = 1
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def addLine(self, line):
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self.lines.append(line)
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self.lineNum+= 1
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def addSection(self, section):
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self.sections.append(section)
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self.sectionPos.append(self.lineNum)
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def expand(self):
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expanded = []
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pos = 0
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if self.repeat == 0:
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return []
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if len(self.sections) == 0:
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return self.lines * self.repeat
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for s, sPos in zip(self.sections, self.sectionPos):
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if pos < sPos:
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expanded += self.lines[pos:sPos]
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pos = sPos
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expanded += s.expand()
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if pos < self.lineNum:
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expanded += self.lines[pos:]
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if self.repeat > 1:
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expanded = expanded * self.repeat
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return expanded
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class verilog_template:
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def __init__(self, template):
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self.template = template
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self.sections = {}
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self.textDict = {}
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self.baseSection = None
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self.expanded = None
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def readTemplate(self):
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lines = []
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with open(self.template, 'r') as f:
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lines = f.readlines()
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self.baseSection = text_section('base', None)
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currentSection = self.baseSection
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for line in lines:
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if line[:2] == '#<':
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section = text_section(line[2:].strip('\n'), currentSection)
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currentSection.addSection(section)
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currentSection = section
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elif line[:2] == '#>' and line[2:].strip('\n') == currentSection.name:
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self.sections[currentSection.name] = currentSection
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currentSection = currentSection.parent
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else:
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currentSection.addLine(line)
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def expand(self):
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self.expanded = self.baseSection.expand()
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def postProcess(self):
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text = ""
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for line in self.expanded:
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if '#$' in line:
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while True:
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indStart = line.find('#$')
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if indStart == -1:
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break
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indEnd = line.find('$#')
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line = line[:indStart] + str(self.textDict[line[indStart + 2:indEnd]]) + line[indEnd + 2:]
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text += line
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elif '#!' in line:
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indLabelStart = line.find('#!') + 2
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indLabelEnd = line.find('!', indLabelStart)
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label = line[indLabelStart:indLabelEnd]
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self.textDict[label] = eval(line[indLabelEnd + 1:-1], self.textDict)
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else:
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text += line
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return text
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def generate(self, filename):
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self.expand()
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text = self.postProcess()
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with open(filename, 'w') as f:
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f.write(text)
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def setSectionRepeat(self, name, repeat):
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self.sections[name].repeat = repeat
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def setTextDict(self, label, value):
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self.textDict[label] = value
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