multi-delay layout pins and routing for them in control logic

compiler/modules/control_logic_delay.py

@@ -390,22 +390,12 @@ class control_logic_delay(design.design):
         offset = vector(0, y_off)
         self.delay_inst.place(offset, mirror="MX")
 
-    def route_delay(self): # TODO
-	pass
-'''
-        out_pos = self.delay_inst.get_pin("out").center()
-        # Connect to the rail level with the vdd rail
-        # Use gated clock since it is in every type of control logic
-        vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch
-        in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos)
-        mid1 = vector(out_pos.x, in_pos.y)
-        self.add_wire(self.m1_stack, [out_pos, mid1, in_pos])
-        self.add_via_center(layers=self.m1_stack,
-                            offset=in_pos)
+    def route_delay(self):
+	delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], 
+			["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
+	
+	slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus)
 
-        # Input from RBL goes to the delay line for futher delay
-        self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
-'''
     # glitch{1-3} are internal timing signals based on different in/out
     # points on the delay chain for adjustable start time and duration
     def create_glitches(self):
@@ -438,11 +428,11 @@ class control_logic_delay(design.design):
         self.row_end_inst.append(self.glitch3_nand_inst)
     
     def route_glitches(self):
-        glitch2_map = zip(["Z"], ["glitch2"])
+        glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"])
 
         self.connect_vertical_bus(glitch2_map, self.glitch2_nand_inst, self.input_bus)
 
-        glitch3_map = zip(["Z"], ["glitch3"])
+        glitch3_map = zip(["A", "B", "Z"], ["delay2", "delay5", "glitch3"])
 
         self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus)
 
@@ -656,7 +646,7 @@ class control_logic_delay(design.design):
     def place_wen_row(self, row):
         x_offset = self.control_x_offset
 
-	x_offset = self.place_util(self.
+	x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
         x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
 
         self.row_end_inst.append(self.w_en_gate_inst)

compiler/modules/multi_delay_chain.py

@@ -18,7 +18,7 @@ class multi_delay_chain(design.design):
     Fanout list contains the electrical effort (fanout) of each stage.
     Usually, this will be constant, but it could have varied fanout.
     Pinout list contains the inverter stages which have an output pin attached.
-    Supplying an empty pinout list will result in an output on the last stage.
+    Supplying an empty pinout list will result in an output only on the last stage.
     """
 
     def __init__(self, name, fanout_list, pinout_list = None):
@@ -41,7 +41,7 @@ class multi_delay_chain(design.design):
         else:
             self.pinout_list = pinout_list
 
-        #would like to sort and check pinout list for valid format but don't have time now
+        # TODO: would like to sort and check pinout list for valid format but don't have time now
         # Check pinout bounds
         # debug.check(self.pinout_list[-1] <= self.rows, 
         #             "Ouput pin cannot exceed delay chain length.")
@@ -58,8 +58,9 @@ class multi_delay_chain(design.design):
         self.create_inverters()
 
     def create_layout(self):
-        # Each stage is a a row
+        # Each stage is a row
         self.height = self.rows * self.inv.height
+
         # The width is determined by the largest fanout plus the driver
         self.width = (max(self.fanout_list) + 1) * self.inv.width
 
@@ -216,12 +217,14 @@ class multi_delay_chain(design.design):
                                         layer="m2",
                                         offset=mid_loc)
 
-        # output is A pin of last load/fanout inverter
-        last_driver_inst = self.driver_inst_list[-1]
-        a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A")
-        self.add_via_stack_center(from_layer=a_pin.layer,
-                                  to_layer="m1",
-                                  offset=a_pin.center())
-        self.add_layout_pin_rect_center(text="out",
-                                        layer="m1",
-                                        offset=a_pin.center())
+	delay_number = 1
+	for pin_number in pinout_list:
+            # output is A pin of last load/fanout inverter
+            output_driver_inst = self.driver_inst_list[pin_number]
+            a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A")
+            self.add_via_stack_center(from_layer=a_pin.layer,
+                                      to_layer="m1",
+                                      offset=a_pin.center())
+            self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)),
+                                            layer="m1",
+                                            offset=a_pin.center())