mirror of https://github.com/VLSIDA/OpenRAM.git
fix coppied functions from replica array to work correctly in capped array
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@ -541,15 +541,13 @@ class capped_replica_bitcell_array(bitcell_base_array):
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"""
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Excludes bits in column from being added to graph except target
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"""
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self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
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self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
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def graph_exclude_replica_col_bits(self):
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"""
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Exclude all replica/dummy cells in the replica columns except the replica bit.
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"""
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for port in self.left_rbl + self.right_rbl:
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self.replica_columns[port].exclude_all_but_replica()
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self.replica_bitcell_array.graph_exclude_replica_col_bits()
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def get_cell_name(self, inst_name, row, col):
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"""
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@ -561,4 +559,4 @@ class capped_replica_bitcell_array(bitcell_base_array):
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"""
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Clears the bit exclusions
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"""
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self.bitcell_array.init_graph_params()
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self.replica_bitcell_array.clear_exclude_bits()
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@ -163,7 +163,7 @@ class local_bitcell_array(bitcell_base_array):
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# FIXME: Replace this with a tech specific parameter
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driver_to_array_spacing = 3 * self.m3_pitch
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wl_offset = vector(0, self.bitcell_array.get_replica_bottom()) # look for offset problems here
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wl_offset = vector(0, self.bitcell_array.get_replica_bottom())
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self.wl_insts[0].place(wl_offset)
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bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0)
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@ -171,7 +171,7 @@ class local_bitcell_array(bitcell_base_array):
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if len(self.all_ports) > 1:
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wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
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self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height) # look for offset problems here
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self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height)
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self.wl_insts[1].place(wl_offset,
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mirror="XY")
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