typo in cs buf netlist function

2022-05-02 11:18:05 -07:00 · 2022-05-02 11:18:05 -07:00 · c4138c9f9b
parent 2b72fbee4e
commit c4138c9f9b
1 changed files with 1 additions and 1 deletions
--- a/compiler/modules/control_logic_delay.py
+++ b/compiler/modules/control_logic_delay.py
@ -444,7 +444,7 @@ class control_logic_delay(design.design):
                                          mod=self.clk_buf_driver)
        self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])

-    def create_clk_buf_row(self):
+    def create_cs_buf_row(self):
        """ Create the multistage and gated chip select buffer  """
        self.cs_buf_inst = self.add_inst(name="csbuf",
                                          mod=self.clk_buf_driver)