mirror of https://github.com/VLSIDA/OpenRAM.git
add most functions needed for delay control logic, fix multi-delay pin order issue
This commit is contained in:
samuelkcrow
parent
45239ca2a9
commit
7d4b718344
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@ -77,7 +77,7 @@ class control_logic_delay(design.design):
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def add_pins(self):
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""" Add the pins to the control logic module. """
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self.add_pin_list(self.input_list + ["clk"] + self.rbl_list, "INPUT")
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self.add_pin_list(self.input_list + ["clk"], "INPUT")
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self.add_pin_list(self.output_list, "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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@ -250,10 +250,8 @@ class control_logic_delay(design.design):
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# List of input control signals
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if self.port_type == "rw":
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self.input_list = ["csb", "web"]
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self.rbl_list = ["rbl_bl"]
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else:
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self.input_list = ["csb"]
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self.rbl_list = ["rbl_bl"]
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if self.port_type == "rw":
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self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
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@ -262,11 +260,9 @@ class control_logic_delay(design.design):
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"]
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elif self.port_type == "r":
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"]
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else:
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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self.internal_bus_list = ["glitch1_bar", "glitch2_bar", "glitch3_bar", "pre_sen", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch
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@ -302,7 +298,7 @@ class control_logic_delay(design.design):
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self.create_gated_clk_buf_row()
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self.create_delay()
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self.create_glitches()
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self.create_glitch3_additional_invs()
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self.create_pre_sen_invs()
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_wen_row()
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@ -338,13 +334,18 @@ class control_logic_delay(design.design):
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row += 1
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self.place_pen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_rbl_delay_row(row)
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row += 1
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self.place_wlen_row(row)
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row += 1
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self.place_glitch1_row(row)
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row += 1
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self.place_glitch2_row(row)
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row += 1
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self.place_glitch3_row(row)
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row += 1
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self.place_pre_sen_row(row)
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row += 1
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control_center_y = self.wl_en_inst.uy() + self.m3_pitch
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control_center_y = self.pre_sen_inv_inst.uy() + self.m3_pitch
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# Delay chain always gets placed at row 4
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self.place_delay(4)
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@ -357,7 +358,8 @@ class control_logic_delay(design.design):
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self.height = height + 2 * self.m1_pitch
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# Max of modules or logic rows
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self.width = max([inst.rx() for inst in self.row_end_inst])
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if (self.port_type == "rw") or (self.port_type == "r"):
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if (self.port_type == "rw") or (self.port_type == "r"):
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# TODO: why not w ports here?
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self.width = max(self.delay_inst.rx(), self.width)
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self.width += self.m2_pitch
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@ -367,7 +369,6 @@ class control_logic_delay(design.design):
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self.route_dffs()
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self.route_wlen()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_rbl_delay()
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_sen()
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@ -382,25 +383,24 @@ class control_logic_delay(design.design):
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""" Create the delay chain """
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self.delay_inst=self.add_inst(name="multi_delay_chain",
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mod=self.multi_delay_chain)
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self.connect_inst(["gated_clk_buf", "out1", "out6", "out7", "out14", "vdd", "gnd"])
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self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "vdd", "gnd"])
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def place_delay(self, row):
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""" Place the replica bitline """
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""" Place the delay chain """
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debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.")
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# It is flipped on X axis
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y_off = row * self.and2.height + self.delay_chain.height
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y_off = row * self.and2.height + self.multi_delay_chain.height
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# Add the RBL above the rows
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# Add to the right of the control rows and routing channel
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offset = vector(0, y_off)
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self.delay_inst.place(offset, mirror="MX")
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def route_delay(self):
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def route_delay(self): # TODO: this
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out_pos = self.delay_inst.get_pin("out").center()
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# Connect to the rail level with the vdd rail
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# Use gated clock since it is in every type of control logic # TODO: git blame whoever wrote this, do they mean every type made by others or is this foreshadowing our future addition of delay/async logic. If the former, seems a bit odd to include something basically explanatory. If the latter, seems odd I'm hearing about it now for the first time, because it begs the question if there are other steps that have been taken to lay groundwork for control logic varieties.
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# Use gated clock since it is in every type of control logic
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vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch
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in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos)
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mid1 = vector(out_pos.x, in_pos.y)
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@ -416,19 +416,19 @@ class control_logic_delay(design.design):
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def create_glitches(self):
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self.glitch1_inv_inst = self.add_inst(name="inv_glitch1",
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mod=self.inv)
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self.connect_inst(["out6", "g1_end", "vdd", "gnd"])
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self.connect_inst(["delay2", "g1_end", "vdd", "gnd"])
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self.glitch2_inv_inst = self.add_inst(name="inv_glitch2",
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mod=self.inv)
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self.connect_inst(["out7", "g2_end", "vdd", "gnd"])
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self.connect_inst(["delay3", "g2_end", "vdd", "gnd"])
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self.glitch3_inv_inst = self.add_inst(name="inv_glitch3",
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mod=self.inv)
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self.connect_inst(["out14", "g3_end", "vdd", "gnd"])
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self.connect_inst(["delay4", "g3_end", "vdd", "gnd"])
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self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1",
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mod=self.nand2)
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self.connect_inst(["out1", "g1_end", "glitch1_bar", "vdd", "gnd"])
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self.connect_inst(["delay1", "g1_end", "glitch1_bar", "vdd", "gnd"])
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self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2",
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mod=self.nand2)
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@ -436,7 +436,38 @@ class control_logic_delay(design.design):
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self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3",
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mod=self.nand2)
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self.connect_inst(["out6", "g3_end", "glitch3_bar", "vdd", "gnd"])
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self.connect_inst(["delay2", "g3_end", "glitch3_bar", "vdd", "gnd"])
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def place_glitch1_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch1_inv_inst, x_offset, row)
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x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch1_nand_inst)
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def place_glitch2_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch2_inv_inst, x_offset, row)
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x_offset = self.place_util(self.glitch2_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch3_nand_inst)
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def place_glitch3_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_inv_inst, x_offset, row)
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x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch3_nand_inst)
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def route_glitches(self): # TODO: this
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glitch1_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus)
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_clk_buf_row(self):
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""" Create the multistage and gated clock buffer """
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@ -444,7 +475,7 @@ class control_logic_delay(design.design):
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mod=self.clk_buf_driver)
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self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
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def create_cs_buf_row(self):
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def create_cs_buf_row(self): # TODO: place and route
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""" Create the multistage and gated chip select buffer """
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self.cs_buf_inst = self.add_inst(name="csbuf",
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mod=self.clk_buf_driver)
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@ -570,10 +601,6 @@ class control_logic_delay(design.design):
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_pen_row(self):
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# FIXME: comment below
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# We use the rbl_bl_delay here to ensure that the p_en is only asserted when the
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# bitlines have already been discharged. Otherwise, it is a combination loop.
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self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst(["glitch1_bar", "p_en_bar", "vdd", "gnd"])
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@ -602,15 +629,23 @@ class control_logic_delay(design.design):
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self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar")
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def create_glitch3_additional_invs(self):
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def create_pre_sen_invs(self):
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""" A pair of inverters to create additional signals from and buffer glitch 3"""
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self.glitch3_buf_inv_inst = self.add_inst(name="inv_glitch3_buf",
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mod=self.inv)
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self.connect_inst(["glitch3_bar", "glitch3_buf", "vdd", "gnd"])
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self.pre_sen_inv = self.add_inst(name="inv_pre_sen",
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self.pre_sen_inv_inst = self.add_inst(name="inv_pre_sen",
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mod=self.inv)
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self.connect_inst(["gltich3_buf", "pre_sen", "vdd", "gnd"])
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self.connect_inst(["glitch3_buf", "pre_sen", "vdd", "gnd"])
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def place_pre_sen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_buf_inv_inst, x_offset, row)
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x_offset = self.place_util(self.pre_sen_inv_inst, x_offset, row)
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self.row_end_inst.append(self.pre_sen_inv_inst)
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def create_sen_row(self):
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""" Create the sense enable buffer. """
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@ -621,10 +656,6 @@ class control_logic_delay(design.design):
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# GATE FOR S_EN
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self.s_en_gate_inst = self.add_inst(name="and_s_en",
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mod=self.sen_and3)
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# FIXME: comment below
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# s_en is asserted in the second half of the cycle during a read.
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# we also must wait until the bitline has been discharged enough for proper sensing
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# hence we use rbl_bl_delay as well.
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self.connect_inst(["pre_sen", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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def place_sen_row(self, row):
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@ -693,7 +724,7 @@ class control_logic_delay(design.design):
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if self.port_type == "rw":
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dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"])
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elif self.port_type == "r":
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dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"])
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dff_out_map = zip(["dout_bar_0"], ["cs"])
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else:
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dff_out_map = zip(["dout_bar_0"], ["cs"])
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self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1])
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@ -1,220 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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class delay_chain(design.design):
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"""
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Generate a delay chain with the given number of stages, fanout, and output pins.
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Fanout list contains the electrical effort (fanout) of each stage.
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Usually, this will be constant, but it could have varied fanout.
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Pinout list contains the inverter stages which have an output pin attached.
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Supplying an empty pinout list will result in an output on the last stage.
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"""
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def __init__(self, name, fanout_list, pinout_list):
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"""init function"""
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super().__init__(name)
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debug.info(1, "creating delay chain {0}".format(str(fanout_list)))
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self.add_comment("fanouts: {0}".format(str(fanout_list)))
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# Two fanouts are needed so that we can route the vdd/gnd connections
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for f in fanout_list:
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debug.check(f>=2, "Must have >=2 fanouts for each stage.")
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# number of inverters including any fanout loads.
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self.fanout_list = fanout_list
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self.rows = len(self.fanout_list)
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# defaults to signle output at end of delay chain
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if len(self.pinout_list) == 0:
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self.pinout_list = [self.rows] # TODO: check for off-by-one here
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else:
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self.pinout_list = pinout_list
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_inverters()
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def create_layout(self):
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# Each stage is a a row
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self.height = self.rows * self.inv.height
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# The width is determined by the largest fanout plus the driver
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self.width = (max(self.fanout_list) + 1) * self.inv.width
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self.place_inverters()
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self.route_inverters()
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self.route_supplies()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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""" Add the pins of the delay chain"""
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self.add_pin("in", "INPUT")
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for pin_stage in self.pinout_list:
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self.add_pin("out{}".format(pin_stage), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.dff = factory.create(module_type="dff_buf")
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dff_height = self.dff.height
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self.inv = factory.create(module_type="pinv",
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height=dff_height)
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def create_inverters(self):
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""" Create the inverters and connect them based on the stage list """
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self.driver_inst_list = []
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self.load_inst_map = {}
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for stage_num, fanout_size in zip(range(self.rows), self.fanout_list):
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# Add the inverter
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cur_driver=self.add_inst(name="dinv{}".format(stage_num),
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mod=self.inv)
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# keep track of the inverter instances so we can use them to get the pins
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self.driver_inst_list.append(cur_driver)
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# Hook up the driver
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stageout_name = "out{}".format(stage_num + 1) # TODO: check for off-by-one here
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if stage_num == 0:
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stagein_name = "in"
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else:
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stagein_name = "out{}".format(stage_num)
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self.connect_inst([stagein_name, stageout_name, "vdd", "gnd"])
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# Now add the dummy loads to the right
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self.load_inst_map[cur_driver]=[]
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for i in range(fanout_size):
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cur_load=self.add_inst(name="dload_{0}_{1}".format(stage_num, i),
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mod=self.inv)
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# Fanout stage is always driven by driver and output is disconnected
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disconnect_name = "n_{0}_{1}".format(stage_num, i)
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self.connect_inst([stageout_name, disconnect_name, "vdd", "gnd"])
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# Keep track of all the loads to connect their inputs as a load
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self.load_inst_map[cur_driver].append(cur_load)
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def place_inverters(self):
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""" Place the inverters and connect them based on the stage list """
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for stage_num, fanout_size in zip(range(self.rows), self.fanout_list):
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if stage_num % 2:
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inv_mirror = "MX"
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inv_offset = vector(0, (stage_num + 1) * self.inv.height)
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else:
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inv_mirror = "R0"
|
||||
inv_offset = vector(0, stage_num * self.inv.height)
|
||||
|
||||
# Add the inverter
|
||||
cur_driver=self.driver_inst_list[stage_num]
|
||||
cur_driver.place(offset=inv_offset,
|
||||
mirror=inv_mirror)
|
||||
|
||||
# Now add the dummy loads to the right
|
||||
load_list = self.load_inst_map[cur_driver]
|
||||
for i in range(fanout_size):
|
||||
inv_offset += vector(self.inv.width, 0)
|
||||
load_list[i].place(offset=inv_offset,
|
||||
mirror=inv_mirror)
|
||||
|
||||
def add_route(self, pin1, pin2):
|
||||
""" This guarantees that we route from the top to bottom row correctly. """
|
||||
pin1_pos = pin1.center()
|
||||
pin2_pos = pin2.center()
|
||||
if pin1_pos.y == pin2_pos.y:
|
||||
self.add_path("m2", [pin1_pos, pin2_pos])
|
||||
else:
|
||||
mid_point = vector(pin2_pos.x, 0.5 * (pin1_pos.y + pin2_pos.y))
|
||||
# Written this way to guarantee it goes right first if we are switching rows
|
||||
self.add_path("m2", [pin1_pos, vector(pin1_pos.x, mid_point.y), mid_point, vector(mid_point.x, pin2_pos.y), pin2_pos])
|
||||
|
||||
def route_inverters(self):
|
||||
""" Add metal routing for each of the fanout stages """
|
||||
|
||||
for i in range(len(self.driver_inst_list)):
|
||||
inv = self.driver_inst_list[i]
|
||||
for load in self.load_inst_map[inv]:
|
||||
# Drop a via on each A pin
|
||||
a_pin = load.get_pin("A")
|
||||
self.add_via_stack_center(from_layer=a_pin.layer,
|
||||
to_layer="m3",
|
||||
offset=a_pin.center())
|
||||
|
||||
# Route an M3 horizontal wire to the furthest
|
||||
z_pin = inv.get_pin("Z")
|
||||
a_pin = inv.get_pin("A")
|
||||
a_max = self.load_inst_map[inv][-1].get_pin("A")
|
||||
self.add_via_stack_center(from_layer=a_pin.layer,
|
||||
to_layer="m2",
|
||||
offset=a_pin.center())
|
||||
self.add_via_stack_center(from_layer=z_pin.layer,
|
||||
to_layer="m3",
|
||||
offset=z_pin.center())
|
||||
self.add_path("m3", [z_pin.center(), a_max.center()])
|
||||
|
||||
# Route Z to the A of the next stage
|
||||
if i + 1 < len(self.driver_inst_list):
|
||||
z_pin = inv.get_pin("Z")
|
||||
next_inv = self.driver_inst_list[i + 1]
|
||||
next_a_pin = next_inv.get_pin("A")
|
||||
y_mid = (z_pin.cy() + next_a_pin.cy()) / 2
|
||||
mid1_point = vector(z_pin.cx(), y_mid)
|
||||
mid2_point = vector(next_a_pin.cx(), y_mid)
|
||||
self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()])
|
||||
|
||||
def route_supplies(self):
|
||||
# Add power and ground to all the cells except:
|
||||
# the fanout driver, the right-most load
|
||||
# The routing to connect the loads is over the first and last cells
|
||||
# We have an even number of drivers and must only do every other
|
||||
# supply rail
|
||||
|
||||
for inst in self.driver_inst_list:
|
||||
load_list = self.load_inst_map[inst]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
pin = load_list[0].get_pin(pin_name)
|
||||
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
|
||||
|
||||
pin = load_list[-2].get_pin(pin_name)
|
||||
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
|
||||
|
||||
def add_layout_pins(self):
|
||||
|
||||
# input is A pin of first inverter
|
||||
# It gets routed to the left a bit to prevent pin access errors
|
||||
# due to the output pin when going up to M3
|
||||
a_pin = self.driver_inst_list[0].get_pin("A")
|
||||
mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy())
|
||||
self.add_via_stack_center(from_layer=a_pin.layer,
|
||||
to_layer="m2",
|
||||
offset=mid_loc)
|
||||
self.add_path(a_pin.layer, [a_pin.center(), mid_loc])
|
||||
|
||||
self.add_layout_pin_rect_center(text="in",
|
||||
layer="m2",
|
||||
offset=mid_loc)
|
||||
|
||||
# output is A pin of last load/fanout inverter
|
||||
last_driver_inst = self.driver_inst_list[-1]
|
||||
a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A")
|
||||
self.add_via_stack_center(from_layer=a_pin.layer,
|
||||
to_layer="m1",
|
||||
offset=a_pin.center())
|
||||
self.add_layout_pin_rect_center(text="out",
|
||||
layer="m1",
|
||||
offset=a_pin.center())
|
||||
|
|
@ -39,14 +39,14 @@ class multi_delay_chain(design.design):
|
|||
if not pinout_list:
|
||||
self.pinout_list = [self.rows] # TODO: check for off-by-one here
|
||||
else:
|
||||
# Set() to sort in ascending order and remove duplicates
|
||||
self.pinout_list = list(set(pinout_list))
|
||||
self.pinout_list = pinout_list
|
||||
|
||||
#would like to sort and check pinout list for valid format but don't have time now
|
||||
# Check pinout bounds
|
||||
debug.check(self.pinout_list[-1] <= self.rows,
|
||||
"Ouput pin cannot exceed delay chain length.")
|
||||
debug.check(self.pinout_list[0] > 0,
|
||||
"Delay chain output pin numbers must be positive")
|
||||
# debug.check(self.pinout_list[-1] <= self.rows,
|
||||
# "Ouput pin cannot exceed delay chain length.")
|
||||
# debug.check(self.pinout_list[0] > 0,
|
||||
# "Delay chain output pin numbers must be positive")
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
|
|
|
|||
Loading…
Reference in New Issue