mirror of https://github.com/VLSIDA/OpenRAM.git
fix mirroring of cap cells in cap rows
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2565305158
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@ -103,7 +103,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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cols=self.column_size + len(self.rbls),
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + len(self.left_rbl),
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column_offset=1,
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mirror=0,
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location="top")
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@ -111,7 +111,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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cols=self.column_size + len(self.rbls),
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + len(self.left_rbl),
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column_offset=1,
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mirror=0,
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location="bottom")
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