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OpenRAM
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Remove factory.reset from all unit tests as we no longer use regress.py.

This commit is contained in:
mrg 2023-03-10 10:44:54 -08:00
parent 4ec8733378
commit c9bf3c1261
53 changed files with 0 additions and 119 deletions
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2
compiler/tests/04_column_mux_pbitcell_test.py
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@ -28,12 +28,10 @@ class column_mux_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking column mux for pbitcell (innermost connections)")
tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking column mux for pbitcell (outermost connections)")
tx = factory.create(module_type="column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)

2
compiler/tests/04_dummy_pbitcell_test.py
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@ -28,7 +28,6 @@ class replica_pbitcell_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Checking dummy bitcell using pbitcell (small cell)")
tx = dummy_pbitcell(name="rpbc")
self.local_check(tx)
@ -37,7 +36,6 @@ class replica_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking dummy bitcell using pbitcell (large cell)")
tx = dummy_pbitcell(name="rpbc")
self.local_check(tx)

10
compiler/tests/04_pbitcell_test.py
View File

@ -26,7 +26,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -34,7 +33,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=0
OPTS.num_w_ports=1
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -42,7 +40,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=0
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -50,7 +47,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -58,7 +54,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=0
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -66,7 +61,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=2
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -74,7 +68,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=0
OPTS.num_w_ports=2
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -82,7 +75,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=0
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -90,7 +82,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=2
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@ -98,7 +89,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=0
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)

1
compiler/tests/04_precharge_1rw_1r_test.py
View File

@ -32,7 +32,6 @@ class precharge_test(openram_test):
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for 1rw1r port 1")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)

3
compiler/tests/04_precharge_pbitcell_test.py
View File

@ -28,17 +28,14 @@ class precharge_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (outermost connections)")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)

2
compiler/tests/04_replica_pbitcell_test.py
View File

@ -28,7 +28,6 @@ class replica_pbitcell_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
tx = replica_pbitcell(name="rpbc")
self.local_check(tx)
@ -37,7 +36,6 @@ class replica_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking replica bitcell using pbitcell (large cell)")
tx = replica_pbitcell(name="rpbc")
self.local_check(tx)

5
compiler/tests/06_hierarchical_decoder_pbitcell_test.py
View File

@ -27,17 +27,14 @@ class hierarchical_decoder_pbitcell_test(openram_test):
OPTS.num_r_ports = 0
openram.setup_bitcell()
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
self.local_check(a)
@ -46,7 +43,6 @@ class hierarchical_decoder_pbitcell_test(openram_test):
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
self.local_check(a)
@ -55,7 +51,6 @@ class hierarchical_decoder_pbitcell_test(openram_test):
a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
self.local_check(a)

1
compiler/tests/07_column_mux_array_pbitcell_test.py
View File

@ -27,7 +27,6 @@ class column_mux_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
a = factory.create(module_type="column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)

1
compiler/tests/08_precharge_array_1rw_1r_test.py
View File

@ -28,7 +28,6 @@ class precharge_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
factory.reset()
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)")
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(pc)

1
compiler/tests/08_wordline_driver_array_pbitcell_test.py
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@ -28,7 +28,6 @@ class wordline_driver_array_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Checking driver (multi-port case)")
tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64)
self.local_check(tx)

1
compiler/tests/09_sense_amp_array_pbitcell_test.py
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@ -28,7 +28,6 @@ class sense_amp_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a)

1
compiler/tests/09_sense_amp_array_spare_cols_test.py
View File

@ -37,7 +37,6 @@ class sense_amp_array_spare_cols_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2, num_spare_cols=2 (multi-port case)")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2, num_spare_cols=2)
self.local_check(a)

1
compiler/tests/10_write_driver_array_pbitcell_test.py
View File

@ -28,7 +28,6 @@ class write_driver_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)

1
compiler/tests/10_write_driver_array_spare_cols_test.py
View File

@ -37,7 +37,6 @@ class write_driver_array_spare_cols_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case and num_spare_cols=3")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3)
self.local_check(a)

1
compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
View File

@ -28,7 +28,6 @@ class write_driver_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
self.local_check(a)

1
compiler/tests/10_write_mask_and_array_pbitcell_test.py
View File

@ -28,7 +28,6 @@ class write_mask_and_array_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
self.local_check(a)

1
compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py
View File

@ -24,7 +24,6 @@ class capped_replica_bitcell_array_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
self.local_check(a)

1
compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py
View File

@ -24,7 +24,6 @@ class capped_replica_bitcell_array_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
self.local_check(a)

1
compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py
View File

@ -24,7 +24,6 @@ class replica_bitcell_array_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
self.local_check(a)

1
compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py
View File

@ -24,7 +24,6 @@ class replica_bitcell_array_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
self.local_check(a)

1
compiler/tests/14_replica_pbitcell_array_test.py
View File

@ -38,7 +38,6 @@ class replica_pbitcell_array_test(openram_test):
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for pbitcell")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
self.local_check(a)

1
compiler/tests/18_port_data_16mux_1rw_1r_test.py
View File

@ -32,7 +32,6 @@ class port_data_1rw_1r_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=16
factory.reset()
c.recompute_sizes()
debug.info(1, "Sixteen way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_16mux_test.py
View File

@ -36,7 +36,6 @@ class port_data_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=16
factory.reset()
c.recompute_sizes()
debug.info(1, "Sixteen way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_2mux_1rw_1r_test.py
View File

@ -31,7 +31,6 @@ class port_data_1rw_1r_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_2mux_test.py
View File

@ -35,7 +35,6 @@ class port_data_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_4mux_1rw_1r_test.py
View File

@ -31,7 +31,6 @@ class port_data_1rw_1r_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_4mux_test.py
View File

@ -35,7 +35,6 @@ class port_data_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_8mux_1rw_1r_test.py
View File

@ -32,7 +32,6 @@ class port_data_1rw_1r_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_8mux_test.py
View File

@ -36,7 +36,6 @@ class port_data_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_nomux_1rw_1r_test.py
View File

@ -30,7 +30,6 @@ class port_data_1rw_1r_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)

1
compiler/tests/18_port_data_nomux_test.py
View File

@ -34,7 +34,6 @@ class port_data_test(openram_test):
num_spare_rows=num_spare_rows)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)

8
compiler/tests/18_port_data_spare_cols_test.py
View File

@ -26,7 +26,6 @@ class port_data_spare_cols_test(openram_test):
num_spare_cols=3)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -34,7 +33,6 @@ class port_data_spare_cols_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -43,7 +41,6 @@ class port_data_spare_cols_test(openram_test):
c.num_words=64
c.words_per_row=4
c.num_spare_cols=3
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -53,7 +50,6 @@ class port_data_spare_cols_test(openram_test):
c.num_words=128
c.words_per_row=8
c.num_spare_cols=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -66,7 +62,6 @@ class port_data_spare_cols_test(openram_test):
c.num_words=16
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -76,7 +71,6 @@ class port_data_spare_cols_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -86,7 +80,6 @@ class port_data_spare_cols_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -97,7 +90,6 @@ class port_data_spare_cols_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)

8
compiler/tests/18_port_data_wmask_1rw_1r_test.py
View File

@ -31,7 +31,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
num_words=16)
c.words_per_row = 1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -39,7 +38,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.num_words = 32
c.words_per_row = 2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -47,7 +45,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.num_words = 64
c.words_per_row = 4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -55,7 +52,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.num_words = 128
c.words_per_row = 8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -68,7 +64,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.num_words = 16
c.words_per_row = 1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -78,7 +73,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
#
c.num_words = 32
c.words_per_row = 2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -88,7 +82,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.num_words = 64
c.words_per_row = 4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -99,7 +92,6 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.word_size = 8
c.num_words = 128
c.words_per_row = 8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)

8
compiler/tests/18_port_data_wmask_test.py
View File

@ -35,7 +35,6 @@ class port_data_wmask_test(openram_test):
num_spare_rows=num_spare_rows)
c.words_per_row = 1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -43,7 +42,6 @@ class port_data_wmask_test(openram_test):
c.num_words = 32
c.words_per_row = 2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -51,7 +49,6 @@ class port_data_wmask_test(openram_test):
c.num_words = 64
c.words_per_row = 4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -59,7 +56,6 @@ class port_data_wmask_test(openram_test):
c.num_words = 128
c.words_per_row = 8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -72,7 +68,6 @@ class port_data_wmask_test(openram_test):
c.num_words = 16
c.words_per_row = 1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -82,7 +77,6 @@ class port_data_wmask_test(openram_test):
#
c.num_words = 32
c.words_per_row = 2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -92,7 +86,6 @@ class port_data_wmask_test(openram_test):
c.num_words = 64
c.words_per_row = 4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
@ -103,7 +96,6 @@ class port_data_wmask_test(openram_test):
c.word_size = 8
c.num_words = 128
c.words_per_row = 8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)

4
compiler/tests/19_multi_bank_test.py
View File

@ -29,7 +29,6 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
@ -37,7 +36,6 @@ class multi_bank_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)
@ -45,7 +43,6 @@ class multi_bank_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)
@ -54,7 +51,6 @@ class multi_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_pmulti_bank_test.py
View File

@ -34,7 +34,6 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
@ -42,7 +41,6 @@ class multi_bank_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)
@ -50,7 +48,6 @@ class multi_bank_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)
@ -59,7 +56,6 @@ class multi_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_psingle_bank_test.py
View File

@ -36,7 +36,6 @@ class psingle_bank_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -44,7 +43,6 @@ class psingle_bank_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -52,7 +50,6 @@ class psingle_bank_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -61,7 +58,6 @@ class psingle_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_16mux_1rw_1r_test.py
View File

@ -32,7 +32,6 @@ class single_bank_1rw_1r_test(openram_test):
num_words=128)
c.words_per_row=16
factory.reset()
c.recompute_sizes()
debug.info(1, "Sixteen way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_16mux_test.py
View File

@ -38,7 +38,6 @@ class single_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=16
factory.reset()
c.recompute_sizes()
debug.info(1, "Sixteen way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_single_bank_1w_1r_test.py
View File

@ -32,7 +32,6 @@ class single_bank_1w_1r_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -40,7 +39,6 @@ class single_bank_1w_1r_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -48,7 +46,6 @@ class single_bank_1w_1r_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -57,7 +54,6 @@ class single_bank_1w_1r_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_2mux_1rw_1r_test.py
View File

@ -33,7 +33,6 @@ class single_bank_1rw_1r_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_2mux_test.py
View File

@ -28,7 +28,6 @@ class single_bank_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)

1
compiler/tests/19_single_bank_4mux_1rw_1r_test.py
View File

@ -33,7 +33,6 @@ class single_bank_1rw_1r_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_4mux_test.py
View File

@ -28,7 +28,6 @@ class single_bank_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)

1
compiler/tests/19_single_bank_8mux_1rw_1r_test.py
View File

@ -34,7 +34,6 @@ class single_bank_1rw_1r_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_8mux_test.py
View File

@ -38,7 +38,6 @@ class single_bank_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_single_bank_global_bitline_test.py
View File

@ -33,7 +33,6 @@ class single_bank_1rw_1r_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -41,7 +40,6 @@ class single_bank_1rw_1r_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -49,7 +47,6 @@ class single_bank_1rw_1r_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create(module_type="bank", sram_config=c)
@ -58,7 +55,6 @@ class single_bank_1rw_1r_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_nomux_1rw_1r_test.py
View File

@ -32,7 +32,6 @@ class single_bank_1rw_1r_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c)

1
compiler/tests/19_single_bank_nomux_test.py
View File

@ -36,7 +36,6 @@ class single_bank_test(openram_test):
num_spare_rows=num_spare_rows)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_single_bank_spare_cols_test.py
View File

@ -28,7 +28,6 @@ class single_bank_spare_cols_test(openram_test):
num_spare_cols=3)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
@ -36,7 +35,6 @@ class single_bank_spare_cols_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)
@ -44,7 +42,6 @@ class single_bank_spare_cols_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)
@ -53,7 +50,6 @@ class single_bank_spare_cols_test(openram_test):
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_single_bank_wmask_1rw_1r_test.py
View File

@ -34,7 +34,6 @@ class single_bank_wmask_1rw_1r_test(openram_test):
num_banks=1)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
@ -42,7 +41,6 @@ class single_bank_wmask_1rw_1r_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)
@ -50,7 +48,6 @@ class single_bank_wmask_1rw_1r_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)
@ -58,7 +55,6 @@ class single_bank_wmask_1rw_1r_test(openram_test):
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/19_single_bank_wmask_test.py
View File

@ -29,7 +29,6 @@ class single_bank_wmask_test(openram_test):
num_banks=1)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
@ -37,7 +36,6 @@ class single_bank_wmask_test(openram_test):
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c)
@ -45,7 +43,6 @@ class single_bank_wmask_test(openram_test):
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("bank", sram_config=c)
@ -53,7 +50,6 @@ class single_bank_wmask_test(openram_test):
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c)

4
compiler/tests/20_sram_2bank_test.py
View File

@ -38,7 +38,6 @@ class sram_2bank_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
@ -54,7 +53,6 @@ class sram_2bank_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
@ -70,7 +68,6 @@ class sram_2bank_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
@ -87,7 +84,6 @@ class sram_2bank_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)