mirror of https://github.com/VLSIDA/OpenRAM.git
TEmplate rework
This commit is contained in:
Bugra Onal
parent
a5728cdecc
commit
9158e92a71
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@ -21,15 +21,8 @@ class verilog:
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def verilog_write(self, verilog_name):
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""" Write a behavioral Verilog model. """
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self.vf = open(verilog_name, "w")
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self.vf.write("// OpenRAM SRAM model\n")
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self.vf.write("// Words: {0}\n".format(self.num_words))
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self.vf.write("// Word size: {0}\n".format(self.word_size))
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if self.write_size:
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self.vf.write("// Write size: {0}\n\n".format(self.write_size))
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else:
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self.vf.write("\n")
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self.template.setSectionRepeat('WRITE_SIZE_CMT', 1)
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try:
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self.vdd_name = spice["power"]
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@ -139,6 +132,10 @@ class verilog:
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self.vf.write(" reg [ADDR_WIDTH-1:0] addr{0}_reg;\n".format(port))
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if port in self.write_ports:
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self.vf.write(" reg [DATA_WIDTH-1:0] din{0}_reg;\n".format(port))
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self.vf.write("`ifdef USE_POWER_PINS\n")
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self.vf.write(" {},\n".format(self.vdd_name))
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self.vf.write(" {},\n".format(self.gnd_name))
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self.vf.write("`endif\n")
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if port in self.read_ports:
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self.vf.write(" reg [DATA_WIDTH-1:0] dout{0};\n".format(port))
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@ -1,153 +0,0 @@
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// OpenRAM SRAM model
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// Words: #$WORDS$#
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// Word size: #$WORD_SIZE$#
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#<WRITE_SIZE_CMT
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// Write size: #$WRITE_SIZE$#
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#>WRITE_SIZE_CMT
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module #$MODULE_NAME$# (
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`ifdef USE_POWER_PINS
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#$VDD$#,
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#$GND$#,
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`endif
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#<WRITE_MASK
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wmask#$PORT_NUM$#,
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#>WRITE_MASK
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#<SPARE_WEN
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spare_wen#$PORT_NUM$#,
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#<SPARE_WEN
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#<RW_PORT
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// Port #$PORT_NUM$#: RW
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clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#$PORT_NUM$#,din#$PORT_NUM$#,dout#$PORT_NUM$#
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#>RW_PORT
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#<R_PORT
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// Port #$PORT_NUM$#: R
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clk#$PORT_NUM#$,csb#$PORT_NUM$#,addr#PORT_NUM$#,dout#PORT_NUM$#
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#>RW_PORT
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#<W_PORT
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// Port #$PORT_NUM$#: W
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clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$#
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#>W_PORT
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);
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#<WMASK_PAR
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parameter NUM_WMASK = #$NUM_WMASK#$ ;
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#>WMASK_PAR
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parameter DATA_WIDTH = #$DATA_WIDTH$# ;
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parameter ADDR_WIDTH = #$ADD_WIDTH$# ;
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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// FIXME: This delay is arbitrary.
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parameter DELAY = 3 ;
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parameter VERBOSE = 1 ; //Set to 0 to only display warnings
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parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
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`ifdef USE_POWER_PINS
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inout #$VDD$#;
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inout #$GND$#;
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`endif
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#<WRITE_MASK
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input [NUM_WMASK-1:0] wmask#$PORT_NUM$#;
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#>WRITE_MASK
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#<SPARE_WEN_SINGLE
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input spare_wen#$PORT_NUM$#;
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#<SPARE_WEN_SINGLE
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#<SPARE_WEN_MULT
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input [#$NUM_SPARE_COL$#-1:0] spare_wen;
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#<SPARE_WEN_MULT
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#<RW_PORT
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input clk#$PORT_NUM#$;
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input csb#$PORT_NUM$#;
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input web#$PORT_NUM$#;
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input [ADDR_WIDTH-1:0] addr#$PORT_NUM$#;
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input [DATA_WIDTH-1:0] din#$PORT_NUM$#;
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output [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
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#>RW_PORT
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#<R_PORT
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input clk#$PORT_NUM#$;
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input csb#$PORT_NUM$#;
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input [ADDR_WIDTH-1:0] addr#$PORT_NUM$#;
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output [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
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#>RW_PORT
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#<W_PORT
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// Port 0: RW
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input clk#$PORT_NUM#$;
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input csb#$PORT_NUM$#;
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input web#$PORT_NUM$#;
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input [ADDR_WIDTH-1:0] addr#$PORT_NUM$#;
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input [DATA_WIDTH-1:0] din#$PORT_NUM$#;
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output [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
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clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$#,dout#PORT_NUM$#
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#>W_PORT
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reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
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#<REGS
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reg csb#$PORT_NUM$#_reg;
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reg web#$PORT_NUM$#_reg;
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reg [NUM_WMASK-1:0] wmask#$PORT_NUM$#_reg;
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reg spare_wen#$PORT_NUM$#_reg;
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reg [#$SPARE_COLS$#-1:0] spare_wen#$PORT_NUM$#_reg;
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reg [ADDR_WIDTH-1:0] addr#$PORT_NUM$#_reg;
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reg [DATA_WIDTH-1:0] din#$PORT_NUM$#_reg;
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reg [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
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#<REGS
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#<FLOPS
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// All inputs are registers
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always @(posedge clk#$PORT_NUM$#)
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begin
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csb#$PORT_NUM$#_reg = csb#$PORT_NUM$#;
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#<WEB_FLOP
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web#$PORT_NUM$#_reg = web#$PORT_NUM$#;
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#>WEB_FLOP
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#<W_MASK_FLOP
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w_mask#$PORT_NUM$#_reg = w_mask#$PORT_NUM$#;
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#>W_MASK_FLOP
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#<SPARE_WEN_FLOP
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spare_wen#$PORT_NUM$#_reg = spare_wen#$PORT_NUM$#;
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#>SPARE_WEN_FLOP
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addr#$PORT_NUM$#_reg = addr#$PORT_NUM$#;
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#<RW_CHECKS
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if (#$WPORT_CONTROL$# && #$RPORT_CONTROL$# && (addr#$WPORT$# == addr#$RPORT$#))
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$display($time," WARNING: Writing and reading addr{0}=%b and addr{1}=%b simultaneously!",addr#$WPORT$#,addr#$RPORT$#);
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#>RW_CHECKS
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if ( !csb0_reg && web0_reg && VERBOSE )
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$display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
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if ( !csb0_reg && !web0_reg && VERBOSE )
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$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
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#>FLOPS
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#<DIN_FLOP
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din#$PORT_NUM$#_reg = din#$PORT_NUM$#;
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#>DIN_FLOP
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#<DOUT_FLOP
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#(T_HOLD) dout#$PORT_NUM$# = #$WORD_SIZE$#'bx;
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#>DOUT_FLOP
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#<RW_VERBOSE
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if ( !csb#$PORT_NUM$#_reg && web#$PORT_NUM$#_reg && VERBOSE )
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$display($time," Reading %m addr#$PORT_NUM$#=%b dout#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,mem[addr#$PORT_NUM$#_reg]);
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#>RW_VERBOSE
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#<R_VERBOSE
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if ( !csb{0}_reg && VERBOSE )
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$display($time," Reading %m addr{0}=%b dout{0}=%b",addr{0}_reg,mem[addr{0}_reg]);
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#>R_VERBOSE
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#<W_VERBOSE
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#>W_VERBOSE
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end
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// Memory Write Block Port 0
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// Write Operation : When web0 = 0, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_WRITE0
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if ( !csb0_reg && !web0_reg ) begin
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mem[addr0_reg][1:0] = din0_reg[1:0];
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end
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end
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// Memory Read Block Port 0
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// Read Operation : When web0 = 1, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_READ0
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if (!csb0_reg && web0_reg)
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dout0 <= #(DELAY) mem[addr0_reg];
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end
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e
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@ -0,0 +1,2 @@
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ERROR: file magic.py: line 358: sram LVS mismatch (results in /tmp/openram_bugra_12868_temp/sram.lvs.report)
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@ -0,0 +1,3 @@
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ERROR: file design.py: line 47: Custom cell pin names do not match spice file:
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['D', 'Q', 'CLK', 'VDD', 'GND'] vs []
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