check delay chain pinout list, add cs_buf to control logic

This commit is contained in:
samuelkcrow 2022-05-02 09:22:54 -07:00
parent 78013d32b7
commit 11ea82e782
2 changed files with 18 additions and 4 deletions

View File

@ -297,6 +297,7 @@ class control_logic_delay(design.design):
""" Create all the instances """
self.create_dffs()
self.create_clk_buf_row()
self.create_cs_buf_row()
self.create_gated_clk_bar_row()
self.create_gated_clk_buf_row()
self.create_delay()
@ -443,6 +444,12 @@ class control_logic_delay(design.design):
mod=self.clk_buf_driver)
self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
def create_clk_buf_row(self):
""" Create the multistage and gated chip select buffer """
self.cs_buf_inst = self.add_inst(name="csbuf",
mod=self.clk_buf_driver)
self.connect_inst(["cs", "cs_buf", "vdd", "gnd"])
def place_clk_buf_row(self, row):
x_offset = self.control_x_offset
@ -543,7 +550,7 @@ class control_logic_delay(design.design):
def create_wlen_row(self):
self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf",
mod=self.wl_en_and)
self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
self.connect_inst(["cs_buf", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
self.wl_en_inst=self.add_inst(name="buf_wl_en",
mod=self.wl_en_driver)

View File

@ -21,7 +21,7 @@ class multi_delay_chain(design.design):
Supplying an empty pinout list will result in an output on the last stage.
"""
def __init__(self, name, fanout_list, pinout_list):
def __init__(self, name, fanout_list, pinout_list = None):
"""init function"""
super().__init__(name)
debug.info(1, "creating delay chain {0}".format(str(fanout_list)))
@ -36,10 +36,17 @@ class multi_delay_chain(design.design):
self.rows = len(self.fanout_list)
# defaults to signle output at end of delay chain
if len(pinout_list) == 0:
if not pinout_list:
self.pinout_list = [self.rows] # TODO: check for off-by-one here
else:
self.pinout_list = pinout_list
# Set() to sort in ascending order and remove duplicates
self.pinout_list = set(pinout_list)
# Check pinout bounds
debug.check(self.pinout_list[-1] <= self.rows,
"Ouput pin cannot exceed delay chain length.")
debug.check(self.pinout_list[0] > 0,
"Delay chain output pin numbers must be positive")
self.create_netlist()
if not OPTS.netlist_only: