mirror of https://github.com/VLSIDA/OpenRAM.git
check delay chain pinout list, add cs_buf to control logic
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parent
78013d32b7
commit
11ea82e782
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@ -297,6 +297,7 @@ class control_logic_delay(design.design):
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""" Create all the instances """
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self.create_dffs()
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self.create_clk_buf_row()
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self.create_cs_buf_row()
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self.create_gated_clk_bar_row()
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self.create_gated_clk_buf_row()
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self.create_delay()
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@ -443,6 +444,12 @@ class control_logic_delay(design.design):
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mod=self.clk_buf_driver)
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self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
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def create_clk_buf_row(self):
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""" Create the multistage and gated chip select buffer """
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self.cs_buf_inst = self.add_inst(name="csbuf",
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mod=self.clk_buf_driver)
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self.connect_inst(["cs", "cs_buf", "vdd", "gnd"])
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def place_clk_buf_row(self, row):
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x_offset = self.control_x_offset
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@ -543,7 +550,7 @@ class control_logic_delay(design.design):
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def create_wlen_row(self):
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self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf",
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mod=self.wl_en_and)
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self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
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self.connect_inst(["cs_buf", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
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self.wl_en_inst=self.add_inst(name="buf_wl_en",
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mod=self.wl_en_driver)
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@ -21,7 +21,7 @@ class multi_delay_chain(design.design):
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Supplying an empty pinout list will result in an output on the last stage.
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"""
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def __init__(self, name, fanout_list, pinout_list):
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def __init__(self, name, fanout_list, pinout_list = None):
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"""init function"""
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super().__init__(name)
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debug.info(1, "creating delay chain {0}".format(str(fanout_list)))
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@ -36,10 +36,17 @@ class multi_delay_chain(design.design):
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self.rows = len(self.fanout_list)
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# defaults to signle output at end of delay chain
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if len(pinout_list) == 0:
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if not pinout_list:
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self.pinout_list = [self.rows] # TODO: check for off-by-one here
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else:
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self.pinout_list = pinout_list
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# Set() to sort in ascending order and remove duplicates
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self.pinout_list = set(pinout_list)
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# Check pinout bounds
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debug.check(self.pinout_list[-1] <= self.rows,
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"Ouput pin cannot exceed delay chain length.")
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debug.check(self.pinout_list[0] > 0,
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"Delay chain output pin numbers must be positive")
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self.create_netlist()
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if not OPTS.netlist_only:
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