mirror of https://github.com/VLSIDA/OpenRAM.git
Write size updated in recompute_sizes
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parent
48fce6485d
commit
2d849aef39
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@ -18,6 +18,7 @@ class sram_config:
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self.word_size = word_size
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self.num_words = num_words
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# Don't add a write mask if it is the same size as the data word
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self.write_size_init = write_size
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if write_size:
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self.write_size = write_size
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else:
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@ -117,6 +118,12 @@ class sram_config:
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self.num_rows = self.num_rows_temp + self.num_spare_rows
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debug.info(1, "Rows: {} Cols: {}".format(self.num_rows_temp, self.num_cols))
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# Fix the write_size
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if self.write_size_init:
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self.write_size = self.write_size_init
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else:
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self.write_size = self.word_size
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# Compute the address and bank sizes
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self.row_addr_size = ceil(log(self.num_rows, 2))
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self.col_addr_size = int(log(self.words_per_row, 2))
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@ -127,8 +134,6 @@ class sram_config:
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+ " Col addr size: {}".format(self.col_addr_size)
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+ " Bank addr size: {}".format(self.bank_addr_size))
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num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
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if num_ports == 1:
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if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0):
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