Move sram and sram_config to openram namespace

__init__.py

@@ -25,3 +25,7 @@ __path__.insert(0, OPENRAM_HOME)
 
 # Import everything in globals.py
 from .globals import *
+# Import classes in the "openram" namespace
+# sram_config should be imported before sram
+from .sram_config import *
+from .sram import *

compiler/modules/__init__.py

@@ -83,6 +83,4 @@ from .write_driver_array import *
 from .write_driver import *
 from .write_mask_and_array import *
 from .sram_1bank import *
-from .sram_config import *
-from .sram import *
 from .internal_base import *

compiler/sram.py

@@ -9,8 +9,7 @@ import os
 import shutil
 import datetime
 from openram import debug
-from openram.characterizer import functional
-from openram.modules import sram_config as config
+from openram import sram_config as config
 from openram import OPTS, print_time
 
 
@@ -50,7 +49,7 @@ class sram():
 
         self.name = name
 
-        from .sram_1bank import sram_1bank as sram
+        from openram.modules.sram_1bank import sram_1bank as sram
 
         self.s = sram(name, sram_config)
 
@@ -73,7 +72,7 @@ class sram():
     def verilog_write(self, name):
         self.s.verilog_write(name)
         if self.num_banks != 1:
-            from .sram_multibank import sram_multibank
+            from openram.modules.sram_multibank import sram_multibank
             mb = sram_multibank(self.s)
             mb.verilog_write(name[:-2] + '_top.v')
 
@@ -95,6 +94,7 @@ class sram():
         # Import this at the last minute so that the proper tech file
         # is loaded and the right tools are selected
         from openram import verify
+        from openram.characterizer import functional
 
         # Save the spice file
         start_time = datetime.datetime.now()

compiler/tests/18_port_data_16mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/18_port_data_16mux_test.py

@@ -19,7 +19,7 @@ class port_data_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/18_port_data_2mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/18_port_data_2mux_test.py

@@ -19,7 +19,7 @@ class port_data_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/18_port_data_4mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/18_port_data_4mux_test.py

@@ -19,7 +19,7 @@ class port_data_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/18_port_data_8mux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/18_port_data_8mux_test.py

@@ -19,7 +19,7 @@ class port_data_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/18_port_data_nomux_1rw_1r_test.py

@@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/18_port_data_nomux_test.py

@@ -19,7 +19,7 @@ class port_data_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/18_port_data_spare_cols_test.py

@@ -19,7 +19,7 @@ class port_data_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         c = sram_config(word_size=8,
                         num_words=16,

compiler/tests/18_port_data_wmask_1rw_1r_test.py

@@ -19,7 +19,7 @@ class port_data_wmask_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/18_port_data_wmask_test.py

@@ -19,7 +19,7 @@ class port_data_wmask_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/19_multi_bank_test.py

@@ -22,7 +22,7 @@ class multi_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_pmulti_bank_test.py

@@ -22,7 +22,7 @@ class multi_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
         OPTS.bitcell = "pbitcell"
 
         # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)

compiler/tests/19_psingle_bank_test.py

@@ -21,7 +21,7 @@ class psingle_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"

compiler/tests/19_single_bank_16mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_16mux_test.py

@@ -21,7 +21,7 @@ class single_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/19_single_bank_1w_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_1w_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_2mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_2mux_test.py

@@ -21,7 +21,7 @@ class single_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_4mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_4mux_test.py

@@ -21,7 +21,7 @@ class single_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_8mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_8mux_test.py

@@ -21,7 +21,7 @@ class single_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/19_single_bank_global_bitline_test.py

@@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_nomux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_nomux_test.py

@@ -21,7 +21,7 @@ class single_bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/19_single_bank_spare_cols_test.py

@@ -21,7 +21,7 @@ class single_bank_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16,

compiler/tests/19_single_bank_wmask_1rw_1r_test.py

@@ -21,7 +21,7 @@ class single_bank_wmask_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/19_single_bank_wmask_test.py

@@ -21,7 +21,7 @@ class single_bank_wmask_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         c = sram_config(word_size=8,
                         write_size=4,

compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py

@@ -21,7 +21,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1

compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py

@@ -21,7 +21,7 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1

compiler/tests/20_psram_1bank_2mux_1w_1r_test.py

@@ -21,7 +21,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 0

compiler/tests/20_psram_1bank_2mux_test.py

@@ -21,7 +21,7 @@ class psram_1bank_2mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1

compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_16mux_test.py

@@ -21,7 +21,7 @@ class sram_1bank_8mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1

compiler/tests/20_sram_1bank_2mux_1w_1r_test.py

@@ -21,7 +21,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1

compiler/tests/20_sram_1bank_2mux_global_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_global_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
         OPTS.local_array_size = 8
 
         if OPTS.tech_name == "sky130":

compiler/tests/20_sram_1bank_2mux_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_2mux_wmask_test.py

@@ -21,7 +21,7 @@ class sram_1bank_2mux_wmask_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_32b_1024_wmask_test.py

@@ -22,7 +22,7 @@ class sram_1bank_32b_1024_wmask_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class sram_1bank_4mux_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_4mux_test.py

@@ -21,7 +21,7 @@ class sram_1bank_4mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_8mux_test.py

@@ -21,7 +21,7 @@ class sram_1bank_8mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py

@@ -21,7 +21,7 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py

@@ -21,7 +21,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/20_sram_1bank_nomux_spare_cols_test.py

@@ -21,7 +21,7 @@ class sram_1bank_nomux_spare_cols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_nomux_test.py

@@ -21,7 +21,7 @@ class sram_1bank_nomux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py

@@ -22,7 +22,7 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_nomux_wmask_test.py

@@ -21,7 +21,7 @@ class sram_1bank_nomux_wmask_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_1bank_ring_test.py

@@ -22,7 +22,7 @@ class sram_1bank_nomux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
         OPTS.supply_pin_type = "ring"
-        from openram.modules import sram_config
+        from openram import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/20_sram_2bank_test.py

@@ -22,7 +22,7 @@ class sram_2bank_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=16,
                         num_words=32,
                         num_banks=2)

compiler/tests/21_hspice_delay_test.py

@@ -31,7 +31,7 @@ class timing_sram_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import delay
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/21_model_delay_test.py

@@ -32,8 +32,8 @@ class model_delay_test(openram_test):
         reload(characterizer)
         from openram.characterizer import delay
         from openram.characterizer import elmore
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/21_ngspice_delay_extra_rows_test.py

@@ -30,7 +30,7 @@ class timing_sram_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import delay
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=1,
                         num_words=16,
                         num_banks=1,

compiler/tests/21_ngspice_delay_global_test.py

@@ -31,7 +31,7 @@ class timing_sram_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import delay
-        from openram.modules import sram_config
+        from openram import sram_config
         OPTS.local_array_size = 2
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/21_ngspice_delay_test.py

@@ -30,7 +30,7 @@ class timing_sram_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import delay
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/21_regression_delay_test.py

@@ -32,8 +32,8 @@ class regression_model_test(openram_test):
         reload(characterizer)
         from openram.characterizer import linear_regression
         from openram.characterizer import neural_network
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/21_xyce_delay_test.py

@@ -30,7 +30,7 @@ class timing_sram_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import delay
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_psram_1bank_2mux_func_test.py

@@ -38,7 +38,7 @@ class psram_1bank_2mux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=32,
                         num_banks=1)

compiler/tests/22_psram_1bank_4mux_func_test.py

@@ -39,7 +39,7 @@ class psram_1bank_4mux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=256,
                         num_banks=1)

compiler/tests/22_psram_1bank_8mux_func_test.py

@@ -39,7 +39,7 @@ class psram_1bank_8mux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=4,
                         num_words=256,
                         num_banks=1)

compiler/tests/22_psram_1bank_nomux_func_test.py

@@ -39,7 +39,7 @@ class psram_1bank_nomux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=32,
                         num_banks=1)

compiler/tests/22_sram_1bank_2mux_func_test.py

@@ -31,7 +31,7 @@ class sram_1bank_2mux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_1bank_2mux_global_func_test.py

@@ -31,7 +31,7 @@ class sram_1bank_2mux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         OPTS.local_array_size = 8
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1

compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py

@@ -31,7 +31,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_1bank_4mux_func_test.py

@@ -31,7 +31,7 @@ class sram_1bank_4mux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_1bank_8mux_func_test.py

@@ -34,7 +34,7 @@ class sram_1bank_8mux_func_test(openram_test):
         if not OPTS.spice_exe:
             debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
 
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py

@@ -35,7 +35,7 @@ class psram_1bank_nomux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=4,
                         num_words=32,
                         num_banks=1)

compiler/tests/22_sram_1bank_nomux_func_test.py

@@ -31,7 +31,7 @@ class sram_1bank_nomux_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py

@@ -31,7 +31,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py

@@ -35,7 +35,7 @@ class sram_wmask_1w_1r_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/22_sram_wmask_func_test.py

@@ -31,7 +31,7 @@ class sram_wmask_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1

compiler/tests/23_lib_sram_linear_regression_test.py

@@ -33,8 +33,8 @@ class lib_sram_linear_regression_test(openram_test):
             num_spare_cols = 0
 
         from openram.characterizer import lib
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,

compiler/tests/23_lib_sram_model_corners_test.py

@@ -32,8 +32,8 @@ class lib_model_corners_lib_test(openram_test):
             num_spare_cols = 0
 
         from openram.characterizer import lib
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,

compiler/tests/23_lib_sram_model_test.py

@@ -32,8 +32,8 @@ class lib_sram_model_test(openram_test):
             num_spare_cols = 0
 
         from openram.characterizer import lib
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,

compiler/tests/23_lib_sram_prune_test.py

@@ -40,8 +40,8 @@ class lib_sram_prune_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,

compiler/tests/23_lib_sram_test.py

@@ -38,8 +38,8 @@ class lib_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,

compiler/tests/24_lef_sram_test.py

@@ -23,8 +23,8 @@ class lef_test(openram_test):
         openram.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1)

compiler/tests/25_verilog_multibank_test.py

@@ -23,8 +23,8 @@ class multibank_verilog_test(openram_test):
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         OPTS.netlist_only=True
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=2)

compiler/tests/25_verilog_sram_test.py

@@ -23,8 +23,8 @@ class verilog_test(openram_test):
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         OPTS.netlist_only=True
-        from openram.modules import sram
-        from openram.modules import sram_config
+        from openram import sram
+        from openram import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1)

compiler/tests/26_sram_pex_test.py

@@ -30,7 +30,7 @@ class sram_pex_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=4,
                         num_words=32,
                         num_banks=1)

compiler/tests/30_openram_back_end_library_test.py

@@ -49,7 +49,7 @@ class openram_back_end_library_test(openram_test):
         OPTS.num_threads = 2
 
         # Create an SRAM using the library
-        from openram.modules import sram
+        from openram import sram
         s = sram()
         s.save()
 

compiler/tests/30_openram_front_end_library_test.py

@@ -50,7 +50,7 @@ class openram_front_end_library_test(openram_test):
         OPTS.num_threads = 2
 
         # Create an SRAM using the library
-        from openram.modules import sram
+        from openram import sram
         s = sram()
         s.save()
 

compiler/tests/50_riscv_1k_1rw1r_func_test.py

@@ -37,7 +37,7 @@ class riscv_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=256,

compiler/tests/50_riscv_1k_1rw_func_test.py

@@ -37,7 +37,7 @@ class riscv_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=256,

compiler/tests/50_riscv_1rw1r_func_test.py

@@ -36,7 +36,7 @@ class riscv_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=32,

compiler/tests/50_riscv_1rw1r_phys_test.py

@@ -22,7 +22,7 @@ class riscv_phys_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
-        from openram.modules import sram_config
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1

compiler/tests/50_riscv_1rw_func_test.py

@@ -44,7 +44,7 @@ class riscv_func_test(openram_test):
         from openram import characterizer
         reload(characterizer)
         from openram.characterizer import functional
-        from openram.modules import sram_config
+        from openram import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=64,