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OpenRAM
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don't route rbl to conrol logic

This commit is contained in:
samuelkcrow 2022-06-25 12:38:07 -07:00
parent 1d6bd78612
commit 3526a57864
2 changed files with 3 additions and 2 deletions
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2
compiler/modules/bank.py
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@ -124,7 +124,7 @@ class bank(design):
for port in self.all_ports:
self.route_bitlines(port)
self.route_rbl(port)
# self.route_rbl(port)
self.route_port_address(port)
self.route_column_address_lines(port)
self.route_control_lines(port)

3
compiler/modules/sram_1bank.py
View File

@ -553,7 +553,7 @@ class sram_1bank(sram_base):
src_pin = self.control_logic_insts[port].get_pin(signal)
dest_pin = self.bank_inst.get_pin(signal + "{}".format(port))
self.connect_vbus(src_pin, dest_pin)
"""
for port in self.all_ports:
# Only input (besides pins) is the replica bitline
src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
@ -566,6 +566,7 @@ class sram_1bank(sram_base):
self.add_via_stack_center(from_layer=dest_pin.layer,
to_layer="m3",
offset=dest_pin.center())
"""
def route_row_addr_dff(self):
"""