mirror of https://github.com/VLSIDA/OpenRAM.git
fix placement bug for cap cells including wrong height from replica array
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5573c6b241
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@ -279,23 +279,23 @@ class capped_replica_bitcell_array(bitcell_base_array):
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# Far top dummy row (first row above array is NOT flipped if even number of rows)
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flip_dummy = (self.row_size + self.rbl[1]) % 2
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dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] - 1 + flip_dummy) + self.replica_bitcell_array_inst.ul()
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dummy_row_offset = self.bitcell_offset.scale(0, flip_dummy) + self.replica_bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.rbl[0] + 1) % 2
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dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] + flip_dummy)
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dummy_row_offset = self.bitcell_offset.scale(0, flip_dummy - 1)
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self.dummy_row_insts[0].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# Far left dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl), -self.rbl[0])
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dummy_col_offset = self.bitcell_offset.scale(-1, -1)
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self.dummy_col_insts[0].place(offset=dummy_col_offset)
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# Far right dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) - 1, -self.rbl[0]) + self.replica_bitcell_array_inst.lr()
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dummy_col_offset = self.bitcell_offset.scale(0, -1) + self.replica_bitcell_array_inst.lr()
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self.dummy_col_insts[1].place(offset=dummy_col_offset)
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def add_layout_pins(self):
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@ -255,7 +255,7 @@ class replica_bitcell_array(bitcell_base_array):
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self.route_supplies()
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self.height = (len(self.rbls) + self.row_size) * self.cell.height
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self.height = (len(self.rbl) + self.row_size) * self.cell.height
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self.width = (len(self.rbls) + self.column_size) * self.cell.width
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self.add_boundary()
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