mirror of https://github.com/VLSIDA/OpenRAM.git
forgot other place with cs_buf
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@ -559,7 +559,7 @@ class control_logic_delay(design.design):
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def create_wlen_row(self):
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self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf",
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mod=self.wl_en_and)
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self.connect_inst(["cs_buf", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
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self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
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self.wl_en_inst=self.add_inst(name="buf_wl_en",
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mod=self.wl_en_driver)
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