mirror of https://github.com/VLSIDA/OpenRAM.git
fix indentation errors, typos, and missing iterator
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parent
3526a57864
commit
1e1ec54275
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@ -368,6 +368,7 @@ class control_logic_delay(design.design):
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self.route_sen()
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self.route_delay()
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self.route_pen()
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self.route_glitches()
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self.route_clk_buf()
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self.route_gated_clk_bar()
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self.route_gated_clk_buf()
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@ -391,10 +392,10 @@ class control_logic_delay(design.design):
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self.delay_inst.place(offset, mirror="MX")
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def route_delay(self):
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delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"],
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delay_map = zip(["in", "delay1", "delay2", "delay3", "delay4", "delay5"], \
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["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
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slef.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus)
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self.connect_vertical_bus(delay_map, self.delay_inst, self.input_bus)
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# glitch{1-3} are internal timing signals based on different in/out
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# points on the delay chain for adjustable start time and duration
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@ -646,7 +647,7 @@ class control_logic_delay(design.design):
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def place_wen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.w_en_gate_inst)
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@ -217,10 +217,10 @@ class multi_delay_chain(design.design):
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layer="m2",
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offset=mid_loc)
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delay_number = 1
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for pin_number in pinout_list:
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delay_number = 1
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for pin_number in self.pinout_list:
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# output is A pin of last load/fanout inverter
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output_driver_inst = self.driver_inst_list[pin_number]
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output_driver_inst = self.driver_inst_list[pin_number - 1]
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a_pin = self.load_inst_map[output_driver_inst][-1].get_pin("A")
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m1",
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@ -228,3 +228,4 @@ class multi_delay_chain(design.design):
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self.add_layout_pin_rect_center(text="delay{}".format(str(delay_number)),
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layer="m1",
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offset=a_pin.center())
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delay_number += 1
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