luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed write_size checks for None

This commit is contained in:
Bugra Onal 2022-07-28 16:45:58 -07:00
parent 6efe974d7b
commit a361d9f7bb
5 changed files with 37 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
compiler/base/verilog.py
View File

@ -24,7 +24,7 @@ class verilog:
self.vf.write("// OpenRAM SRAM model\n")
self.vf.write("// Words: {0}\n".format(self.num_words))
self.vf.write("// Word size: {0}\n".format(self.word_size))
if self.write_size:
if self.write_size != self.word_size:
self.vf.write("// Write size: {0}\n\n".format(self.write_size))
else:
self.vf.write("\n")
@ -56,14 +56,14 @@ class verilog:
self.vf.write("// Port {0}: W\n".format(port))
if port in self.readwrite_ports:
self.vf.write(" clk{0},csb{0},web{0},".format(port))
if self.write_size:
if self.write_size != self.word_size:
self.vf.write("wmask{},".format(port))
if self.num_spare_cols > 0:
self.vf.write("spare_wen{0},".format(port))
self.vf.write("addr{0},din{0},dout{0}".format(port))
elif port in self.write_ports:
self.vf.write(" clk{0},csb{0},".format(port))
if self.write_size:
if self.write_size != self.word_size:
self.vf.write("wmask{},".format(port))
if self.num_spare_cols > 0:
self.vf.write("spare_wen{0},".format(port))
@ -75,7 +75,7 @@ class verilog:
self.vf.write(",\n")
self.vf.write("\n );\n\n")
if self.write_size:
if self.write_size != self.word_size:
self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
self.vf.write(" parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks))
self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size + self.num_spare_cols))
@ -128,7 +128,7 @@ class verilog:
if port in self.readwrite_ports:
self.vf.write(" reg web{0}_reg;\n".format(port))
if port in self.write_ports:
if self.write_size:
if self.write_size != self.word_size:
self.vf.write(" reg [NUM_WMASKS-1:0] wmask{0}_reg;\n".format(port))
if self.num_spare_cols > 1:
self.vf.write(" reg [{1}:0] spare_wen{0}_reg;".format(port, self.num_spare_cols - 1))
@ -152,7 +152,7 @@ class verilog:
if port in self.readwrite_ports:
self.vf.write(" web{0}_reg = web{0};\n".format(port))
if port in self.write_ports:
if self.write_size:
if self.write_size != self.word_size:
self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port))
if self.num_spare_cols:
self.vf.write(" spare_wen{0}_reg = spare_wen{0};\n".format(port))
@ -172,13 +172,13 @@ class verilog:
self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
if port in self.readwrite_ports:
self.vf.write(" if ( !csb{0}_reg && !web{0}_reg && VERBOSE )\n".format(port))
if self.write_size:
if self.write_size != self.word_size:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port))
else:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port))
elif port in self.write_ports:
self.vf.write(" if ( !csb{0}_reg && VERBOSE )\n".format(port))
if self.write_size:
if self.write_size != self.word_size:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port))
else:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port))
@ -196,7 +196,7 @@ class verilog:
self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port))
if port in self.write_ports:
if self.write_size:
if self.write_size != self.word_size:
self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port))
if self.num_spare_cols == 1:
self.vf.write(" input spare_wen{0}; // spare mask\n".format(port))
@ -221,7 +221,7 @@ class verilog:
else:
self.vf.write(" if (!csb{0}_reg) begin\n".format(port))
if self.write_size:
if self.write_size != self.word_size:
for mask in range(0, self.num_wmasks):
lower = mask * self.write_size
upper = lower + self.write_size - 1

4
compiler/modules/bank.py
View File

@ -27,7 +27,7 @@ class bank(design):
self.sram_config = sram_config
sram_config.set_local_config(self)
if self.write_size:
if self.write_size != self.word_size:
self.num_wmasks = int(ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
@ -769,7 +769,7 @@ class bank(design):
din_name = "din{0}_{1}".format(port, row)
self.copy_layout_pin(self.port_data_inst[port], data_name, din_name)
if self.write_size:
if self.write_size != self.word_size:
for row in range(self.num_wmasks):
wmask_name = "bank_wmask_{}".format(row)
bank_wmask_name = "bank_wmask{0}_{1}".format(port, row)

2
compiler/modules/sram.py
View File

@ -36,7 +36,7 @@ class sram():
self.name = name
from sram_1bank import sram_1bank as sram
from .sram_1bank import sram_1bank as sram
self.s = sram(name, sram_config)

36
compiler/modules/sram_1bank.py
View File

@ -8,14 +8,14 @@
from base import vector
from base import channel_route
from router import router_tech
from globals import OPTS
from globals import OPTS, print_time
import datetime
import debug
from math import ceil
from importlib import reload
from design import design
from verilog import verilog
from lef import lef
from base import design
from base import verilog
from base import lef
from sram_factory import factory
from tech import spice
@ -34,7 +34,7 @@ class sram_1bank(design, verilog, lef):
self.bank_insts = []
if self.write_size:
if self.write_size != self.word_size:
self.num_wmasks = int(ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
@ -254,9 +254,9 @@ class sram_1bank(design, verilog, lef):
# Do not route the power supply (leave as must-connect pins)
return
elif OPTS.route_supplies == "grid":
from supply_grid_router import supply_grid_router as router
from router import supply_grid_router as router
else:
from supply_tree_router import supply_tree_router as router
from router import supply_tree_router as router
rtr=router(layers=self.supply_stack,
design=self,
bbox=bbox,
@ -356,7 +356,7 @@ class sram_1bank(design, verilog, lef):
pins_to_route.append("addr{0}[{1}]".format(port, bit + self.col_addr_size))
if port in self.write_ports:
if self.write_size:
if self.write_size != self.word_size:
for bit in range(self.num_wmasks):
pins_to_route.append("wmask{0}[{1}]".format(port, bit))
@ -367,7 +367,7 @@ class sram_1bank(design, verilog, lef):
for bit in range(self.num_spare_cols):
pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
from signal_escape_router import signal_escape_router as router
from router import signal_escape_router as router
rtr=router(layers=self.m3_stack,
design=self,
bbox=bbox)
@ -491,19 +491,15 @@ class sram_1bank(design, verilog, lef):
self.data_dff = factory.create("dff_array", module_name="data_dff", rows=1, columns=self.word_size + self.num_spare_cols)
if self.write_size:
if self.write_size != self.word_size:
self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks)
if self.num_spare_cols:
self.spare_wen_dff = factory.create("dff_array", module_name="spare_wen_dff", rows=1, columns=self.num_spare_cols)
# Create bank decoder
# if(self.num_banks > 1):
# self.add_multi_bank_modules()
self.bank_count = 0
c = reload(__import__(OPTS.control_logic))
c = reload(__import__('modules.' + OPTS.control_logic))
self.mod_control_logic = getattr(c, OPTS.control_logic)
# Create the control logic module for each port type
@ -796,7 +792,7 @@ class sram_1bank(design, verilog, lef):
if self.col_addr_dff:
self.col_addr_dff_insts = self.create_col_addr_dff()
if self.write_size:
if self.write_size != self.word_size:
self.wmask_dff_insts = self.create_wmask_dff()
self.data_dff_insts = self.create_data_dff()
else:
@ -940,7 +936,7 @@ class sram_1bank(design, verilog, lef):
self.col_addr_pos[port] = vector(x_offset, 0)
if port in self.write_ports:
if self.write_size:
if self.write_size != self.word_size:
# Add the write mask flops below the write mask AND array.
self.wmask_pos[port] = vector(x_offset,
y_offset)
@ -992,7 +988,7 @@ class sram_1bank(design, verilog, lef):
self.spare_wen_dff_insts[port].place(self.spare_wen_pos[port], mirror="MX")
x_offset = self.spare_wen_dff_insts[port].lx()
if self.write_size:
if self.write_size != self.word_size:
# Add the write mask flops below the write mask AND array.
self.wmask_pos[port] = vector(x_offset - self.wmask_dff_insts[port].width,
y_offset)
@ -1059,7 +1055,7 @@ class sram_1bank(design, verilog, lef):
start_layer=pin_layer)
if port in self.write_ports:
if self.write_size:
if self.write_size != self.word_size:
for bit in range(self.num_wmasks):
self.add_io_pin(self.wmask_dff_insts[port],
"din_{}".format(bit),
@ -1371,7 +1367,7 @@ class sram_1bank(design, verilog, lef):
# Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay.
for inst in self.data_dff_insts:
self.graph_inst_exclude.add(inst)
if self.write_size:
if self.write_size != self.word_size:
for inst in self.wmask_dff_insts:
self.graph_inst_exclude.add(inst)
if self.num_spare_cols:

16
compiler/modules/write_driver_array.py
View File

@ -38,7 +38,7 @@ class write_driver_array(design):
else:
self.num_spare_cols = num_spare_cols
if self.write_size:
if self.write_size != self.word_size:
self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
self.create_netlist()
@ -82,10 +82,10 @@ class write_driver_array(design):
for i in range(self.word_size + self.num_spare_cols):
self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT")
self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT")
if self.write_size:
if self.write_size != self.word_size:
for i in range(self.num_wmasks + self.num_spare_cols):
self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
elif self.num_spare_cols and not self.write_size:
elif self.num_spare_cols and self.write_size == self.word_size:
for i in range(self.num_spare_cols + 1):
self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
else:
@ -110,7 +110,7 @@ class write_driver_array(design):
self.local_insts.append(self.add_inst(name=name,
mod=self.driver))
if self.write_size:
if self.write_size != self.word_size:
self.connect_inst([self.data_name + "_{0}".format(index),
self.get_bl_name() + "_{0}".format(index),
self.get_br_name() + "_{0}".format(index),
@ -121,7 +121,7 @@ class write_driver_array(design):
w = 0
windex+=1
elif self.num_spare_cols and not self.write_size:
elif self.num_spare_cols and self.write_size == self.word_size:
self.connect_inst([self.data_name + "_{0}".format(index),
self.get_bl_name() + "_{0}".format(index),
self.get_br_name() + "_{0}".format(index),
@ -135,7 +135,7 @@ class write_driver_array(design):
for i in range(self.num_spare_cols):
index = self.word_size + i
if self.write_size:
if self.write_size != self.word_size:
offset = self.num_wmasks
else:
offset = 1
@ -205,7 +205,7 @@ class write_driver_array(design):
width=br_pin.width(),
height=br_pin.height())
if self.write_size:
if self.write_size != self.word_size:
for bit in range(self.num_wmasks):
inst = self.local_insts[bit * self.write_size]
en_pin = inst.get_pin(inst.mod.en_name)
@ -229,7 +229,7 @@ class write_driver_array(design):
layer="m1",
offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
elif self.num_spare_cols and not self.write_size:
elif self.num_spare_cols and self.write_size == self.word_size:
# shorten enable rail to accomodate those for spare write drivers
left_inst = self.local_insts[0]
left_en_pin = left_inst.get_pin(inst.mod.en_name)