mirror of https://github.com/VLSIDA/OpenRAM.git
Remove regress.py and skip_tests for Makefile option instead.
This commit is contained in:
mrg
parent
1f3bdd598a
commit
5c173551ec
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@ -15,28 +15,14 @@ TEST_STAMPS= $(addsuffix .ok,$(TEST_BASES))
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OPENRAM_DIR = $(OPENRAM_HOME)/tests
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RESULTS_DIR = $(OPENRAM_DIR)/results
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# Use % for all techs:
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# %/test.py
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# or a specific tech:
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# freepdk45/test.py
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BROKEN_STAMPS = \
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sky130/01_library_test.ok \
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sky130/04_column_mux_pbitcell_test.ok \
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sky130/04_dummy_pbitcell_test.ok \
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sky130/04_pbitcell_test.ok \
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sky130/04_pnand4_test.ok \
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sky130/04_pand4_test.ok \
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sky130/04_precharge_pbitcell_test.ok \
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sky130/04_replica_pbitcell_test.ok \
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sky130/05_pbitcell_array_test.ok \
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sky130/05_bitcell_array_test.ok \
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sky130/05_bitcell_array_1rw_1r_test.ok \
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sky130/05_dummy_array_test.ok \
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%/06_hierarchical_decoder_4096row_test.ok \
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sky130/07_column_mux_array_pbitcell_test.ok \
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sky130/19_pmulti_bank_test.ok \
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sky130/19_psingle_bank_test.ok \
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sky130/19_bank_select_pbitcell_test.ok \
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%/19_single_bank_16mux_1rw_1r_test.ok \
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%/19_single_bank_16mux_test.ok \
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%/20_sram_1bank_16mux_1rw_1r_test.ok \
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@ -47,11 +33,6 @@ BROKEN_STAMPS = \
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%/20_psram_1bank_2mux_test.ok \
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%/21_hspice_delay_test.ok \
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%/21_hspice_setuphold_test.ok \
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sky130/20_psram_1bank_4mux_1rw_1r_test.ok \
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sky130/22_psram_1bank_2mux_func_test.ok \
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sky130/22_psram_1bank_4mux_func_test.ok \
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sky130/22_psram_1bank_8mux_func_test.ok \
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sky130/22_psram_1bank_nomux_func_test.ok \
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%/22_psram_1bank_2mux_func_test.ok \
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%/22_psram_1bank_4mux_func_test.ok \
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%/22_psram_1bank_8mux_func_test.ok \
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@ -66,11 +47,6 @@ BROKEN_STAMPS = \
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%/22_sram_1bank_nomux_sparecols_func_test.ok \
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%/22_sram_1bank_wmask_1rw_1r_func_test.ok \
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%/22_sram_wmask_func_test.ok \
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sky130/23_lib_sram_linear_regression_test.ok \
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sky130/23_lib_sram_model_corners_test.ok \
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sky130/23_lib_sram_model_test.ok \
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sky130/23_lib_sram_prune_test.ok \
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sky131/23_lib_sram_test.ok \
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%/26_hspice_pex_pinv_test.ok \
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%/27_verilog_multibank_test.ok \
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%/50_riscv_1k_1rw1r_func_test.ok \
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@ -87,6 +63,35 @@ BROKEN_STAMPS = \
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%/50_riscv_512b_1rw_func_test.ok \
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%/50_riscv_8k_1rw1r_func_test.ok \
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%/50_riscv_8k_1rw_func_test.ok \
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freepdk45/21_xyce_delay_test.ok \
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scn4m_subm/19_single_bank_global_bitline_test.ok \
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scn4m_subm/21_xyce_delay_test.ok \
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sky130/01_library_test.ok \
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sky130/04_column_mux_pbitcell_test.ok \
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sky130/04_dummy_pbitcell_test.ok \
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sky130/04_pbitcell_test.ok \
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sky130/04_pnand4_test.ok \
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sky130/04_pand4_test.ok \
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sky130/04_precharge_pbitcell_test.ok \
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sky130/04_replica_pbitcell_test.ok \
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sky130/05_pbitcell_array_test.ok \
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sky130/05_bitcell_array_test.ok \
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sky130/05_bitcell_array_1rw_1r_test.ok \
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sky130/05_dummy_array_test.ok \
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sky130/07_column_mux_array_pbitcell_test.ok \
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sky130/19_pmulti_bank_test.ok \
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sky130/19_psingle_bank_test.ok \
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sky130/19_bank_select_pbitcell_test.ok \
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sky130/20_psram_1bank_4mux_1rw_1r_test.ok \
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sky130/22_psram_1bank_2mux_func_test.ok \
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sky130/22_psram_1bank_4mux_func_test.ok \
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sky130/22_psram_1bank_8mux_func_test.ok \
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sky130/22_psram_1bank_nomux_func_test.ok \
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sky130/23_lib_sram_linear_regression_test.ok \
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sky130/23_lib_sram_model_corners_test.ok \
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sky130/23_lib_sram_model_test.ok \
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sky130/23_lib_sram_prune_test.ok \
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sky131/23_lib_sram_test.ok
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gettech = $(word 1,$(subst /, ,$*))
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getfile = $(word 2,$(subst /, ,$*))
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@ -1,113 +0,0 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import re
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import unittest
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import sys, os
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from openram import globals
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from subunit import ProtocolTestCase, TestProtocolClient
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from testtools import ConcurrentTestSuite
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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from testutils import *
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header(__file__, OPTS.tech_name)
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# get a list of all files in the tests directory
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files = os.listdir(sys.path[0])
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# load a file with all tests to skip in a given technology
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# since tech_name is dynamically loaded, we can't use @skip directives
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try:
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skip_file_name = "{0}/tests/skip_tests_{1}.txt".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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skip_file = open(skip_file_name, "r")
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skip_tests = skip_file.read().splitlines()
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for st in skip_tests:
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debug.warning("Skipping: " + st)
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except FileNotFoundError:
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skip_tests = []
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# assume any file that ends in "test.py" in it is a regression test
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nametest = re.compile("test\.py$", re.IGNORECASE)
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all_tests = list(filter(nametest.search, files))
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filtered_tests = list(filter(lambda i: i not in skip_tests, all_tests))
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filtered_tests.sort()
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num_threads = OPTS.num_threads
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def partition_unit_tests(suite, num_threads):
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partitions = [list() for x in range(num_threads)]
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for index, test in enumerate(suite):
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partitions[index % num_threads].append(test)
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return partitions
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def fork_tests(num_threads):
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results = []
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test_partitions = partition_unit_tests(suite, num_threads)
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suite._tests[:] = []
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def do_fork(suite):
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for test_partition in test_partitions:
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test_suite = unittest.TestSuite(test_partition)
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test_partition[:] = []
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c2pread, c2pwrite = os.pipe()
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pid = os.fork()
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if pid == 0:
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# PID of 0 is a child
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try:
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# Open a stream to write to the parent
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stream = os.fdopen(c2pwrite, 'wb', 0)
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os.close(c2pread)
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sys.stdin.close()
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test_suite_result = TestProtocolClient(stream)
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test_suite.run(test_suite_result)
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except EBADF:
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try:
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stream.write(traceback.format_exc())
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finally:
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os._exit(1)
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os._exit(0)
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else:
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# PID >0 is the parent
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# Collect all of the child streams and append to the results
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os.close(c2pwrite)
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stream = os.fdopen(c2pread, 'rb', 0)
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test = ProtocolTestCase(stream)
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results.append(test)
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return results
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return do_fork
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# import all of the modules
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filenameToModuleName = lambda f: os.path.splitext(f)[0]
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moduleNames = map(filenameToModuleName, filtered_tests)
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modules = map(__import__, moduleNames)
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suite = unittest.TestSuite()
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load = unittest.defaultTestLoader.loadTestsFromModule
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suite.addTests(map(load, modules))
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test_runner = unittest.TextTestRunner(verbosity=2, stream=sys.stderr)
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if num_threads == 1:
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final_suite = suite
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else:
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final_suite = ConcurrentTestSuite(suite, fork_tests(num_threads))
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test_result = test_runner.run(final_suite)
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# import verify
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# verify.print_drc_stats()
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# verify.print_lvs_stats()
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# verify.print_pex_stats()
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sys.exit(not test_result.wasSuccessful())
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@ -1 +0,0 @@
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21_xyce_delay_test.py
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@ -1,2 +0,0 @@
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19_single_bank_global_bitline_test.py
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21_xyce_delay_test.py
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@ -1,86 +0,0 @@
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04_dummy_pbitcell_test.py
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04_pbitcell_test.py
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04_precharge_pbitcell_test.py
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04_replica_pbitcell_test.py
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04_column_mux_pbitcell_test.py
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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07_column_mux_array_pbitcell_test.py
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08_wordline_driver_array_pbitcell_test.py
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08_wordline_driver_array_test.py
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09_sense_amp_array_test_pbitcell.py
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09_sense_amp_array_test.py
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_driver_array_wmask_test.py
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10_write_mask_and_array_pbitcell_test.py
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10_write_mask_and_array_test.py
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12_tri_gate_array_test.py
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14_replica_pbitcell_array_test.py
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14_replica_bitcell_array_test.py
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14_replica_column_test.py
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14_replica_column_1rw_1r_test.py
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18_port_address_test.py
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18_port_data_test.py
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18_port_data_wmask_test.py
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19_bank_select_pbitcell_test.py
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19_bank_select_test.py
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19_psingle_bank_test.py
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19_bank_select_pbitcell_test.py
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19_pmulti_bank_test.py
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19_multi_bank_test.py
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19_psingle_bank_test.py
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19_single_bank_1w_1r_test.py
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19_single_bank_wmask_1rw_1r_test.py
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19_single_bank_1rw_1r_test.py
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19_single_bank_test.py
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19_single_bank_wmask_test.py
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20_psram_1bank_2mux_1rw_1w_test.py
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20_psram_1bank_2mux_1rw_1w_wmask_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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20_psram_1bank_2mux_test.py
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20_psram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_2mux_1w_1r_test.py
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20_sram_1bank_2mux_test.py
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20_sram_1bank_2mux_wmask_test.py
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20_sram_1bank_32b_1024_wmask_test.py
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20_sram_1bank_4mux_test.py
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20_sram_1bank_8mux_test.py
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20_sram_1bank_nomux_test.py
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20_sram_1bank_nomux_wmask_test.py
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20_sram_2bank_test.py
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21_hspice_delay_test.py
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21_hspice_setuphold_test.py
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21_model_delay_test.py
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21_ngspice_delay_test.py
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21_ngspice_setuphold_test.py
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22_psram_1bank_2mux_func_test.py
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22_psram_1bank_4mux_func_test.py
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22_psram_1bank_8mux_func_test.py
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22_psram_1bank_nomux_func_test.py
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22_sram_1bank_2mux_func_test.py
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22_sram_1bank_4mux_func_test.py
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22_sram_1bank_8mux_func_test.py
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22_sram_1bank_nomux_func_test.py
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22_sram_1rw_1r_1bank_nomux_func_test.py
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22_sram_wmask_func_test.py
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23_lib_sram_model_corners_test.py
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23_lib_sram_model_test.py
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23_lib_sram_prune_test.py
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23_lib_sram_test.py
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24_lef_sram_test.py
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25_verilog_sram_test.py
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26_hspice_pex_pinv_test.py
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26_ngspice_pex_pinv_test.py
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26_pex_test.py
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30_openram_back_end_test.py
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30_openram_front_end_test.py
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