mirror of https://github.com/VLSIDA/OpenRAM.git
fix pin shape issue
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d460eacfcc
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@ -231,7 +231,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.width = self.dummy_col_insts[1].rx()
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self.height = self.dummy_row_insts[1].uy()
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self.copy_layout_pins()
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self.add_layout_pins()
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self.route_supplies()
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@ -298,21 +298,26 @@ class capped_replica_bitcell_array(bitcell_base_array):
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dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) - 1, -self.rbl[0]) + self.replica_bitcell_array_inst.lr()
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self.dummy_col_insts[1].place(offset=dummy_col_offset)
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def copy_layout_pins(self):
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excluded_pins = ["vdd", "gnd"]
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excluded_pins.extend(self.unused_wordline_names)
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for pin_name in self.replica_bitcell_array.get_pin_names():
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if pin_name in excluded_pins:
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continue
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# move pins to edges of cap cells
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if "wl" in pin_name:
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pin_offset = self.bitcell_offset.scale(-1, 0)
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else:
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pin_offset = self.bitcell_offset.scale(0, -1)
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def add_layout_pins(self):
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for pin_name in self.used_wordline_names + self.all_bitline_names:
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pin = self.replica_bitcell_array_inst.get_pin(pin_name)
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self.copy_layout_pin(instance=self.replica_bitcell_array_inst,
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pin_name=pin_name,
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relative_offset=pin_offset)
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if "wl" in pin_name:
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# wordlines
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pin_offset = pin.ll().scale(0, 1)
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pin_width = self.width
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pin_height = pin.height()
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else:
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# bitlines
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pin_offset = pin.ll().scale(1, 0)
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pin_width = pin.width()
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pin_height = self.height
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin_offset,
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width=pin_width,
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height=pin_height)
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def route_supplies(self):
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