Fixed the bad commas with post-process regex

compiler/modules/sram_multibank.py

@@ -1,15 +1,8 @@
 from template import template
 from globals import OPTS
-<<<<<<< HEAD
-<<<<<<< HEAD
 import os
 from math import ceil, log
-=======
->>>>>>> 3dd65b1a (modified template engine & sram multibank class)
-=======
-import os
-from math import ceil, log
->>>>>>> 22c01d7f (Multibank file generation (messy))
+import re
 
 
 class sram_multibank:
@@ -31,10 +24,17 @@ class sram_multibank:
             'data_width': sram.word_size,
             'addr_width': sram.bank_addr_size + ceil(log(sram.num_banks, 2)),
             'bank_sel': ceil(log(sram.num_banks, 2)),
-            'num_wmask': sram.num_wmasks
+            'num_wmask': sram.num_wmasks,
+            'write_size': sram.write_size
             }
 
     def verilog_write(self, name):
         template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v")
         t = template(template_filename, self.dict)
         t.write(name)
+        with open(name, 'r') as f:
+            text = f.read()
+            badComma = re.compile(',(\s*\n\s*\);)')
+            text = badComma.sub(r'\1', text)
+        with open(name, 'w') as f:
+            f.write(text)

compiler/modules/sram_multibank_template.v

@@ -9,9 +9,9 @@ module {{ module_name }}  (
     addr{{ port }},
     din{{ port }},
     csb{{ port }},
-    {% if write_size > 1 %}
+{% if num_wmask > 1 %}
     wmask{{ port }},
-    {% endif %}
+{% endif %}
     web{{ port }},
     dout{{ port }},
 {% endfor %}
@@ -26,9 +26,9 @@ module {{ module_name }}  (
     addr{{ port }},
     din{{ port }},
     csb{{ port }},
-    {% if write_size > 1 %}
+{% if num_wmask > 1 %}
     wmask{{ port }},
-    {% endif %}
+{% endif %}
     web{{ port }},
 {% endfor %}
   );
@@ -49,9 +49,9 @@ module {{ module_name }}  (
   input [DATA_WIDTH - 1: 0] din{{ port }};
   input csb{{ port }};
   input web{{ port }};
-  {% if write_size > 1 %}
+{% if num_wmask > 1 %}
   input [NUM_WMASK - 1 : 0] wmask{{ port }};
-  {% endif %}
+{% endif %}
   output reg [DATA_WIDTH - 1 : 0] dout{{ port }};
 {% endfor %}
 {% for port in r_ports %}
@@ -66,9 +66,9 @@ module {{ module_name }}  (
   input [DATA_WIDTH - 1: 0] din{{ port }};
   input csb{{ port }};
   input web{{ port }};
-  {% if write_size > 1 %}
+{% if num_wmask > 1 %}
   input [NUM_WMASK - 1 : 0] wmask{{ port }};
-  {% endif %}
+{% endif %}
 {% endfor %}
 
 {% for port in ports %}
@@ -96,9 +96,9 @@ module {{ module_name }}  (
     .din{{ port }}(din{{ port }}),
     .csb{{ port }}(csb{{ port }}_bank{{ bank }}),
     .web{{ port }}(web{{ port }}_bank{{ bank }}),
-    {% if write_size > 1 %}
+{% if num_wmask > 1 %}
     .wmask{{ port }}(wmask{{ port }}),
-    {% endif %}
+{% endif %}
     .dout{{ port }}(dout{{ port }}_bank{{ bank }}),
 {% endfor %}
 {% for port in r_ports %}
@@ -112,9 +112,9 @@ module {{ module_name }}  (
     .addr{{ port }}(addr{{ port }}[ADDR_WIDTH - BANK_SEL - 1 : 0]),
     .din{{ port }}(din{{ port }}),
     .csb{{ port }}(csb{{ port }}_bank{{ bank }}),
-    {% if write_size > 1 %}
+{% if num_wmask > 1 %}
     .wmask{{ port }}(wmask{{ port }}),
-    {% endif %}
+{% endif %}
     .web{{ port }}(web{{ port }}_bank{{ bank }}),
 {% endfor %}
   );