mirror of https://github.com/VLSIDA/OpenRAM.git
fix typo in wordline var
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@ -85,7 +85,7 @@ class local_bitcell_array(bitcell_base_array):
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self.array_wordline_inputs = []
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self.wordline_names = self.bitcell_array.bitcell_wordline_names
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self.all_wordline_names = self.bitcell_array.bitcell_all_wordline_names
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self.all_wordline_names = self.bitcell_array.all_bitcell_wordline_names
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self.bitline_names = self.bitcell_array.bitcell_bitline_names
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self.all_bitline_names = self.bitcell_array.all_bitcell_bitline_names
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