mirror of https://github.com/VLSIDA/OpenRAM.git
Add empty build_graph() for dummy bitcells
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@ -21,3 +21,6 @@ class dummy_bitcell_1port(bitcell_base):
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super().__init__(name, prop=props.bitcell_1port)
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debug.info(2, "Create dummy bitcell")
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def build_graph(self, graph, inst_name, port_nets):
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""" Adds edges based on inputs/outputs. Overrides base class function. """
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pass
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@ -21,3 +21,6 @@ class dummy_bitcell_2port(bitcell_base):
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super().__init__(name, prop=props.bitcell_2port)
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debug.info(2, "Create dummy bitcell 2 port object")
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def build_graph(self, graph, inst_name, port_nets):
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""" Adds edges based on inputs/outputs. Overrides base class function. """
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pass
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