mirror of https://github.com/VLSIDA/OpenRAM.git
Move is_non_inverting graph code to bitcell_base class to work with pbitcell too.
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@ -29,7 +29,3 @@ class bitcell_1port(bitcell_base):
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"""
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self.add_graph_edges(graph, port_nets)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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@ -99,8 +99,3 @@ class bitcell_2port(bitcell_base):
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# Port 1 edges
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graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
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graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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@ -265,3 +265,15 @@ class bitcell_base(design):
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delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m)
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return delay
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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debug.error("Must override build_graph function in bitcell base class.")
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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