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make capped array name more descriptive and add x mode to tests

This commit is contained in:
samuelkcrow 2023-01-17 10:09:45 -08:00
parent b5cddb9394
commit 78cabf9ca3
4 changed files with 7 additions and 7 deletions
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2
compiler/modules/capped_bitcell_array.py → compiler/modules/capped_replica_bitcell_array.py
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@ -14,7 +14,7 @@ from openram import OPTS
from .bitcell_base_array import bitcell_base_array
class capped_bitcell_array(bitcell_base_array):
class capped_replica_bitcell_array(bitcell_base_array):
"""
Creates a replica bitcell array then adds the row and column caps to all
sides of a bitcell array.

4
compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py → compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py Normal file → Executable file
View File

@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@ -26,7 +26,7 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array left and right replica for dp cell")
a = factory.create(module_type="capped_bitcell_array",
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],

4
compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py → compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py Normal file → Executable file
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@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@ -26,7 +26,7 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
openram.setup_bitcell()
debug.info(2, "Testing 4x4 left replica array for dp cell")
a = factory.create(module_type="capped_bitcell_array",
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],

4
compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py → compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py Normal file → Executable file
View File

@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@ -26,7 +26,7 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
openram.setup_bitcell()
debug.info(2, "Testing 4x4 non-replica array for dp cell")
a = factory.create(module_type="capped_bitcell_array",
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1])