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update local/global tests for no rbls

This commit is contained in:
Sam Crow 2023-03-09 14:37:07 -08:00
parent 41344a980b
commit 710f0fbae5
4 changed files with 28 additions and 18 deletions
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4
compiler/tests/15_global_bitcell_array_1rw_1r_test.py
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@ -32,10 +32,6 @@ class global_bitcell_array_test(openram_test):
a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
self.local_check(a)
# debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
# a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
# self.local_check(a)
openram.end_openram()

11
compiler/tests/15_global_bitcell_array_test.py → compiler/tests/15_global_bitcell_array_1rw_test.py
View File

@ -17,18 +17,19 @@ from openram import OPTS
# @unittest.skip("SKIPPING 05_global_bitcell_array_test")
class global_bitcell_array_test(openram_test):
class global_bitcell_array_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
# debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
# a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
# self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4)
a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
self.local_check(a)
openram.end_openram()

18
compiler/tests/15_local_bitcell_array_1rw_1r_test.py
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@ -28,19 +28,23 @@ class local_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica")
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica columns or dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica column but with dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with left replica column and dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with right replica column and dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with both replica columns and dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)

13
compiler/tests/15_local_bitcell_array_test.py → compiler/tests/15_local_bitcell_array_1rw_test.py
View File

@ -17,13 +17,22 @@ from openram import OPTS
# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
class local_bitcell_array_test(openram_test):
class local_bitcell_array_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column or dummy row")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column but with dummy row")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0])
self.local_check(a)