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exclude rbl connection in sram base for delay control logic

This commit is contained in:
samuelkcrow 2022-06-01 09:37:06 -07:00
parent 7d4b718344
commit ef2c9fe296
1 changed files with 2 additions and 1 deletions
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3
compiler/modules/sram_base.py
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@ -717,7 +717,8 @@ class sram_base(design, verilog, lef):
if port in self.readwrite_ports:
temp.append("web{}".format(port))
temp.append("clk{}".format(port))
temp.append("rbl_bl{}".format(port))
if OPTS.control_logic != "control_logic_delay":
temp.append("rbl_bl{}".format(port))
# Outputs
if port in self.read_ports: