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OpenRAM
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1157 Commits

Author SHA1 Message Date
Jacob Walker aea3c0ad01 passing drc/lvs on 4x4 rom array 2023-03-30 11:30:50 -07:00
Jacob Walker a3e271f6fb reoriented cell and added tap cell 2023-03-30 11:30:50 -07:00
Jacob Walker 7309af7e29 base and dummy array alignment in sky130 2023-03-30 11:30:50 -07:00
Jacob Walker d7ac26a053 array generation and bitline routing with array module 2023-03-30 11:30:50 -07:00
Jacob Walker 4db5c3be26 basic nmos array, for nand rom 2023-03-30 11:30:50 -07:00
Sam Crow e20f28580f support no rbls in local array 2023-03-09 14:44:05 -08:00
Sam Crow 41344a980b change array modules to allow rbl=[0, 0] 2023-03-09 10:23:28 -08:00
mrg 58f1b55e08 Over-ride build_graph in row/col caps to remove incorrect graph error. 2023-03-01 09:25:56 -08:00
samuelkcrow e90964fbda update copyright 2023-02-21 14:04:31 -08:00
samuelkcrow ad4b4f66dc use capped array to create banks 2023-02-21 09:58:46 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
samuelkcrow 52dcd81a08 use left_rbl instead of rbl to calculate replica column mirroring (column offset) 2023-02-20 17:28:24 -08:00
samuelkcrow 51a7161cd7 fix mirroring of cap cells in cap rows 2023-02-14 10:59:00 -08:00
samuelkcrow 2565305158 fix positional getters 2023-02-13 18:45:21 -08:00
samuelkcrow 8d6d8f2f8c revert variable names to those inherited from bitcell base array 2023-02-13 18:45:21 -08:00
samuelkcrow 2948b08e66 copy rbl default values logic from lower array modules 2023-02-06 20:04:54 -08:00
samuelkcrow 796b1913cf fix typo in wordline var 2023-02-06 20:01:49 -08:00
samuelkcrow c256a5eb44 fix coppied functions from replica array to work correctly in capped array 2023-02-06 19:57:42 -08:00
samuelkcrow 4a22c5c56f add instance offset to capped array offset getters 2023-02-06 19:40:37 -08:00
samuelkcrow 92a9a1729e untested update to get_cell_name function used by characterizer 2023-02-06 19:19:02 -08:00
samuelkcrow 3dac89d041 fixing named variables passed between array modules 2023-02-04 21:06:41 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 2f795f8068 fix height calculation bug for replica array 2023-01-26 17:38:24 -08:00
samuelkcrow 03adf94b6a fix offsets to match original replica array, and make array translation statically sized 2023-01-26 12:31:14 -08:00
samuelkcrow 8fc93bc91a point local array to new capped array module 2023-01-24 11:09:57 -08:00
samuelkcrow ebe163c57e fix placement bug for cap cells including wrong height from replica array 2023-01-24 11:07:52 -08:00
samuelkcrow 5573c6b241 fix pin shape issue 2023-01-18 22:44:32 -08:00
samuelkcrow d460eacfcc standardize rbl arguments interface 2023-01-18 22:43:37 -08:00
samuelkcrow 78c4ba5fc0 clean up comments 2023-01-18 21:01:30 -08:00
samuelkcrow 7021b80506 remove unused side argument from side routing functions 2023-01-18 20:36:36 -08:00
samuelkcrow 8522f32e43 radically simplify unused wordline routing code... bit of a facepalm tbh 2023-01-18 20:32:40 -08:00
samuelkcrow 78cabf9ca3 make capped array name more descriptive and add x mode to tests 2023-01-17 10:20:16 -08:00
samuelkcrow b5cddb9394 fix remaining lvs issues by adding an offset to pins gotten from subinstances and appropriately grounding wls in cap cells 2023-01-16 17:54:17 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
samuelkcrow d8e0f4275d fix capped array after merge with dev 2022-12-14 14:20:54 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
samuelkcrow 119bcb9197 route unused wordlines (still failing lvs) 2022-12-14 08:12:55 -08:00
samuelkcrow d224c06b25 placement positions problem fixed, incorrect w,h calculations were the problem 2022-12-10 19:03:55 -08:00
Eren Dogan 6a4f6cbbed Move sram and sram_config to openram namespace 2022-12-02 15:28:06 -08:00
Eren Dogan 7396899769 Add empty build_graph() for dummy bitcells 2022-12-02 12:14:40 -08:00
samuelkcrow 68fb4e3c63 introduced some other bugs but scmos tiling is correct 2022-12-02 09:42:33 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan e15454ebb9 Make sram_config optional for sram 2022-11-29 10:33:32 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
samuelkcrow ac8a15acc0 fix get_replica_top and get_replica_left return values 2022-11-21 17:42:50 -08:00
samuelkcrow 5a82c45a33 Change how lists of BLs and WLs are named and organized for proper connection between these modules 2022-10-24 20:08:13 -07:00
mrg 9b6eb4a120 Fix whitespace 2022-10-20 16:38:23 -07:00
mrg 8fd08916a1 Move is_non_inverting graph code to bitcell_base class to work with pbitcell too. 2022-10-20 15:16:10 -07:00
samuelkcrow 55d89fbae8 copy supply pins to top level in replica array, now passing tests 2022-10-19 17:13:54 -07:00
samuelkcrow f9419e8ff7 fix self.rbls and fix handling of rbl WLs (kinda) 2022-10-17 20:51:42 -07:00
samuelkcrow a1ca7c312d remove grounded WLs from replica array 2022-10-11 11:43:26 -07:00
samuelkcrow cfd52a6065 fix offsets so array ends up at 0,0 2022-09-26 14:24:16 -07:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
samuelkcrow f1f18b3b54 replica code working but failing lvs 2022-09-07 19:32:25 -07:00
samuelkcrow 3ef52789be first pass splitting replica array into capped and replica array modules 2022-09-07 12:39:35 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal a7c6406d0d Changed verilog file naming convention 2022-08-18 10:36:54 -07:00
Bugra Onal 1a23d156c0 remove references to bank_sel 2022-08-18 10:33:46 -07:00
Bugra Onal 242d90f543 Code format fixes 2022-08-13 13:58:53 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal 6ba2a9bca7 Make sure num_wmasks is 0 when no wmask is generated 2022-08-10 16:35:39 -07:00
Bugra Onal f743b1f068 Convert to new modules format 2022-08-10 16:34:49 -07:00
Bugra Onal 2d849aef39 Write size updated in recompute_sizes 2022-08-10 15:36:41 -07:00
Bugra Onal 48fce6485d write_size None initialization fixed 2022-08-04 16:37:21 -07:00
Bugra Onal 2ed107f9ff Fix the total addr_size 2022-08-04 16:36:26 -07:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
samuelkcrow 1177df6193 move most of place_instances to base 2022-08-01 10:33:48 -07:00
Bugra Onal 7fe0f647ef fix 2022-07-28 17:00:16 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 6efe974d7b Delete sram_base form rebase 2022-07-28 16:02:39 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
Bugra Onal 02d8eca640 Fix indentation 2022-07-28 15:07:19 -07:00
Bugra Onal 36e23dc80f Moved template module to new modules folder 2022-07-28 15:05:34 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
samuelkcrow 1c8aeaa68a fix imports 2022-07-27 11:09:10 -07:00
samuelkcrow 2ff9ea4f78 move generic functions from control_logic module to new control_logic_base module 2022-07-26 23:22:02 -07:00
mrg 69d5731d67 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-07-22 13:47:19 -07:00
samuelkcrow b82213caff use packages for imports in modules 2022-07-22 12:56:47 -07:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
samuelkcrow 5fa0689c02 fix drc error in wlen_row 2022-07-21 19:35:02 -07:00
samuelkcrow 08ac1c176a connect in pin via m2 instead of m3, passes lvs now 2022-07-21 19:35:02 -07:00
samuelkcrow 12c58b0457 use spice names for delay chain output pins in layout 2022-07-21 19:35:02 -07:00
samuelkcrow 73021be8eb copy vertical bus spacing from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 2611468dd7 replace route_supply with route supplies from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 9182ad7c61 add m4 spacing for route_rails same as control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 7f52e63aca route glitch3 to inverter on wen row 2022-07-21 19:35:02 -07:00
samuelkcrow 231dca5b51 route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus 2022-07-21 19:35:02 -07:00
samuelkcrow 74bf3770d9 move pins to m3, route in pin down to avoid m3 collision 2022-07-21 19:35:02 -07:00
samuelkcrow fd7a7c2564 routing mistake in route_wlen 2022-07-21 19:35:02 -07:00
samuelkcrow 1e1ec54275 fix indentation errors, typos, and missing iterator 2022-07-21 19:35:02 -07:00
samuelkcrow 3526a57864 don't route rbl to conrol logic 2022-07-21 19:35:02 -07:00
samuelkcrow 1d6bd78612 multi-delay layout pins and routing for them in control logic 2022-07-21 19:35:01 -07:00
samuelkcrow d7b1368115 all route functions except for delay 2022-07-21 19:35:01 -07:00
samuelkcrow 63ea1588c1 more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement 2022-07-21 19:35:01 -07:00
samuelkcrow 0a3c1dd9b8 remove pre_sen entirely, move inverter to wl_en row, complete placement functions 2022-07-21 19:35:01 -07:00
samuelkcrow 7b4af87fda remove the cs_buf function call... smh 2022-07-21 19:35:01 -07:00
samuelkcrow 5edb511dab try it without pre_sen 2022-07-21 19:35:01 -07:00
samuelkcrow 71f241f660 remove remaining cs_buf functions 2022-07-21 19:35:01 -07:00
samuelkcrow 67c1560df0 forgot other place with cs_buf 2022-07-21 19:35:01 -07:00
samuelkcrow fede082b80 cs instead of cs_buf now that everything else is working 2022-07-21 19:35:01 -07:00
samuelkcrow 30b9c2fc25 remove glitch inverters from placement functions, move glitch1 to pen row 2022-07-21 19:35:01 -07:00
samuelkcrow 606260dd68 use odd number inverter chains from delay chain for delay instead of external inverters 2022-07-21 19:35:01 -07:00
samuelkcrow b9b57ab6b3 double length of delay chain as well 2022-07-21 19:35:01 -07:00
samuelkcrow 06254fae72 forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops 2022-07-21 19:35:01 -07:00
samuelkcrow ef2c9fe296 exclude rbl connection in sram base for delay control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 7d4b718344 add most functions needed for delay control logic, fix multi-delay pin order issue 2022-07-21 19:35:01 -07:00
samuelkcrow 45239ca2a9 use cs_buf for sense amp on r ports instead of cs 2022-07-21 19:35:01 -07:00
samuelkcrow c4138c9f9b typo in cs buf netlist function 2022-07-21 19:35:01 -07:00
samuelkcrow 2b72fbee4e bug fix list vs set 2022-07-21 19:35:01 -07:00
samuelkcrow 11ea82e782 check delay chain pinout list, add cs_buf to control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 78013d32b7 hard-code multi-delay stages 2022-07-21 19:35:01 -07:00
samuelkcrow 62a65f8053 all remaining spice for delay control 2022-07-21 19:35:01 -07:00
samuelkcrow 66502fc5dc new control logic module with no more rbl logic, added glitches so far 2022-07-21 19:35:01 -07:00
samuelkcrow b05a721fb5 spice for delay chain with all inverter outputs as pins 2022-07-21 19:35:01 -07:00
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg ff7ceaf92d Fix syntax error for module scope in row/col caps. 2022-07-13 17:19:09 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg cf03454ecf Don't add wdriver_sel_n pins which aren't used. 2022-06-10 09:18:40 -07:00
mrg d30f05a1ae Update power layer on li for sky130 2022-06-08 17:19:26 -07:00
mrg 280582d4d6 Add missing via in dff array 2022-06-08 14:24:17 -07:00
mrg ad6633ddca Update versions of tools. Fix supply bug in predecode. 2022-06-08 13:50:25 -07:00
mrg 8c85230033 Remove experimental power option. 2022-05-23 10:08:35 -07:00
mrg 735d66c9f1 Start dff array supplies on first rather than second bit. 2022-05-17 15:54:54 -07:00
mrg 3e02a0e7df Update column decoder and dff array supplies 2022-05-17 15:49:50 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 4345136d1a Fix offsets for local bitcell arrays. 2022-05-13 10:46:00 -07:00
mrg 357f967a93 Leave supply routing to new helper functions. 2022-05-11 11:01:14 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg f8f3f16b1f Move delay line supply strap for pin access. 2022-05-02 16:42:14 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00