mirror of https://github.com/VLSIDA/OpenRAM.git
base and dummy array alignment in sky130
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d7ac26a053
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@ -40,7 +40,7 @@ class rom_base_array(bitcell_base_array):
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self.place_ptx()
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#self.route_horizontal_pins(insts=self.cell_inst.values(), layer=self.route_layer, name="S")
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self.route_bitlines()
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#self.route_bitlines()
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#self.route_wordlines()
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self.route_supplies()
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@ -51,17 +51,26 @@ class rom_base_array(bitcell_base_array):
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#def add_pins(self):
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def add_boundary(self):
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self.width = self.nmos.width * self.column_size
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self.height = self.nmos.height * self.row_size
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self.width = self.cell.width * self.column_size
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self.height = self.cell.height * self.row_size
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super().add_boundary()
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def add_modules(self):
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self.nmos = factory.create(module_type="ptx", tx_type="nmos", add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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temp = self.nmos.width
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self.nmos.width = self.nmos.height + self.nmos.poly_extend_active
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self.nmos.height = temp
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# base cell, nmos tx that represents a 1
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self.cell = factory.create(module_type="rom_base_cell")
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# "dummy" cells represent 0
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#dummy cell with no contacts
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self.dummy_nc = factory.create(module_type="rom_dummy_cell")
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#dummy cell with drain contact
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self.dummy_dc = factory.create(module_type="rom_dummy_cell", drain_contact=True)
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#dummy cell with source contact
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self.dummy_sc = factory.create(module_type="rom_dummy_cell", source_contact=True)
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#dummy cell with all contacts
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self.dummy_ac = factory.create(module_type="rom_dummy_cell", source_contact=True, drain_contact=True)
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def create_instances(self):
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self.cell_inst = {}
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self.cell_list = []
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@ -75,11 +84,31 @@ class rom_base_array(bitcell_base_array):
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if(self.data[row][col] == 1):
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.nmos, rotate=90)
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mod=self.cell)
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row_list.append(self.cell_inst[row, col])
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self.connect_inst(self.get_bitcell_pins(row, col))
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else: row_list.append(None)
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self.connect_inst(["vdd", "gnd", "gnd"])
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else:
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if col < self.column_size - 1 and col > 0 and self.data[row][col + 1] == 1 and self.data[row][col - 1] == 1:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_ac)
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elif col > 0 and self.data[row][col - 1] == 1:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_dc)
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elif col < self.column_size - 1 and self.data[row][col + 1] == 1:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_sc)
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else:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_nc)
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self.connect_inst([])
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row_list.append(self.cell_inst[row, col])
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self.cell_list.append(row_list)
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@ -94,34 +123,40 @@ class rom_base_array(bitcell_base_array):
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def place_ptx(self):
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self.cell_pos = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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# rows are bitlines
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for row in range(self.row_size):
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# columns are word lines
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for col in range(self.column_size):
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#cell_x = (self.nmos.height + self.nmos.poly_extend_active) * col
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#cell_y = (self.nmos.width + 2 * self.nmos.active_contact_to_gate + self.nmos.contact_width) * row
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cell_x = self.nmos.width * col
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cell_y = self.nmos.height * row
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print(self.nmos.height + self.nmos.poly_extend_active)
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cell_x = (self.cell.width) * col
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cell_y = row * (self.cell.height)
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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#cell_x = self.cell.width * col
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#cell_y = self.cell.height * row
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#print(self.nmos.height + self.nmos.poly_extend_active)
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if(self.data[row][col] == 1):
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pass
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self.cell_pos[row, col] = self.nmos.active_offset.scale(1, 0) \
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+ vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col], rotate=90)
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self.add_label("S_{}_{}".format(row,col), self.route_layer, self.cell_inst[row, col].get_pin("S").center())
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self.add_label("D", self.route_layer, self.cell_inst[row, col].get_pin("D").center())
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#self.add_label("S_{}_{}".format(row,col), self.route_layer, self.cell_inst[row, col].center())
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#self.add_label("D", self.route_layer, self.cell_inst[row, col].center())
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else:
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#else:
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#poly_offset = (self.nmos.contact_offset + vector(0.5 * self.nmos.active_contact.width + 0.5 * self.nmos.poly_width + self.nmos.active_contact_to_gate, 0)) + (0, cell_y)
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poly_offset = (cell_x, cell_y)
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#poly_offset = (cell_x, cell_y)
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#print(cell_x,cell_y)
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self.add_rect(layer="poly",
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offset=poly_offset,
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width=self.nmos.height + self.nmos.poly_extend_active,
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height=self.nmos.poly_width
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)
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#self.add_rect(layer="poly",
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# offset=poly_offset,
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# width=self.nmos.height + self.nmos.poly_extend_active,
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# height=self.nmos.poly_width
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# )
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@ -0,0 +1,81 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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from .rom_dummy_cell import rom_dummy_cell
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from base import design
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from base import vector
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from globals import OPTS
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from sram_factory import factory
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from tech import drc
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class rom_base_cell(rom_dummy_cell):
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def __init__(self, name="", cell_name=None):
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super().__init__(name, cell_name)
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#self.route_layer= route_layer
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#self.create_netlist()
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#self.create_layout()
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def create_netlist(self):
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print("using base cell netlist creation")
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self.add_pins()
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self.add_nmos()
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self.create_nmos()
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def create_layout(self):
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self.setup_drc_offsets()
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self.place_nmos()
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self.add_boundary()
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print(self.height)
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print(self.width)
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def add_pins(self):
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pin_list = ["bl_h", "bl_l", "wl"]
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dir_list = ["INOUT", "GROUND", "INPUT"]
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self.add_pin_list(pin_list, dir_list)
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def create_nmos(self):
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self.cell_inst = self.add_inst( name=self.name,
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mod=self.nmos,
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rotate=90)
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self.connect_inst(["bl_h", "wl", "bl_l", "gnd"])
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def place_nmos(self):
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poly_offset = vector(0.5 * self.nmos.active_contact.width + self.nmos.active_contact_to_gate,
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self.nmos.poly_height)
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nmos_offset = vector(- 0.5 * self.nmos.contact_width - self.active_enclose_contact, self.nmos.poly_extend_active)
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# add rect of poly to account for offset from drc spacing
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self.add_rect("poly", poly_offset, self.nmos.poly_width, self.poly_extend_active_spacing )
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self.cell_inst.place(nmos_offset)
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self.add_label("S", self.route_layer, self.cell_inst.get_pin("S").center())
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self.add_label("D", self.route_layer, self.cell_inst.get_pin("D").center())
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@ -0,0 +1,125 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from base import design
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from base import vector
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from globals import OPTS
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from sram_factory import factory
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from tech import drc
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class rom_dummy_cell(design):
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def __init__(self, name="", cell_name=None, source_contact=False, drain_contact=False):
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super().__init__(name, cell_name)
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self.route_layer = "m1"
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self.source_contact=source_contact
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self.drain_contact=drain_contact
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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#creates nmos for layout dimensions
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self.add_nmos()
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#set height and width such that the cell will tile perfectly by only ofsetting in the array by its width and height
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def create_layout(self):
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self.setup_drc_offsets()
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self.add_boundary()
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self.add_poly()
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self.add_metal()
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#poly_offset =
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# vector(0.5 * self.nmos.active_contact.width + 0.5 * self.nmos.poly_width + self.nmos.active_contact_to_gate, 0)
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#self.add_rect( layer="poly",
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# offset=poly_offset,
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# height=self.nmos.height + self.nmos.poly_extend_active,
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# width=self.nmos.poly_width
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# )
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self.add_label("0,0", self.route_layer)
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#self.add_wire( layers=self.route_layer)
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#self.add_rect( layer=self.route_layer)
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# Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules
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def setup_drc_offsets(self):
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#nmos contact to gate distance
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self.contact_to_gate = 0.5 * (self.nmos.width - 2 * self.nmos.contact_width - self.nmos.poly_width - 2 * self.active_enclose_contact)
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#height offset to account for active-to-active spacing between adjacent bitlines
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self.poly_extend_active_spacing = abs( 2 * self.nmos.poly_extend_active - drc("active_to_active") )
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#contact to contact distance, minimum cell width before drc offsets
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self.base_width = self.nmos.width - 2 * self.active_enclose_contact - self.nmos.contact_width
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#width offset to account for active-to-active spacing between cells on the same bitline
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#this is calculated as a negative value
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self.cell_diffusion_offset = ((self.base_width - 2 * self.active_enclose_contact - self.nmos.contact_width) - drc("active_to_active")) * 0.5
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# width offset to account for poly-active spacing between base and dummy cells on the same bitline
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self.poly_active_offset = 0.5 * (self.base_width - 2 * self.cell_diffusion_offset - (self.poly_width + 2 * self.active_enclose_contact + self.nmos.contact_width)) - self.poly_to_active
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def add_boundary(self):
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#cell height with offsets applied
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self.height = self.nmos.height + self.poly_extend_active_spacing + 2 * self.nmos.poly_extend_active
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# cell width with offsets applied, if the offsets are positive (greater than 0) they are not applied
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self.width = self.base_width - min(self.cell_diffusion_offset, 0) - min(self.poly_active_offset, 0)
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super().add_boundary()
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def add_poly(self):
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poly_x = 0.5 * self.nmos.contact_width + self.contact_to_gate
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self.add_rect("poly", vector(poly_x, 0), self.poly_width, self.height)
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def add_metal(self):
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wire_x = min(self.cell_diffusion_offset, 0) + min(self.poly_active_offset, 0)
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wire_y = 0.5 * (self.height - self.poly_extend_active_spacing)
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wire_start = vector( wire_x, wire_y )
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wire_end = vector(self.width, wire_y)
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if self.route_layer == 'm1':
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if self.drain_contact:
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self.add_via_center(self.li_stack, [wire_x, wire_y])
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if self.source_contact:
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self.add_via_center(self.li_stack, [self.width, wire_y])
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self.add_path(self.route_layer, [wire_start, wire_end])
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def add_nmos(self):
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#used only for layout constants
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self.nmos = factory.create(module_type="ptx",
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tx_type="nmos"
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)
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@ -24,7 +24,7 @@ class rom_array_test(openram_test):
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debug.info(2, "Testing 4x4 array for rom cell")
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data = [[1, 1, 1, 1], [1, 1, 1, 1], [1, 0, 1, 1], [1, 1, 1, 0]]
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data = [[1, 0, 0, 0], [0, 1, 1, 1], [1, 0, 1, 1], [1, 1, 0, 1]]
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a = factory.create(module_type="rom_base_array", cols=4, rows=4, bitmap=data)
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self.local_check(a)
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