base and dummy array alignment in sky130

This commit is contained in:
Jacob Walker 2022-08-12 19:51:08 -07:00
parent d7ac26a053
commit 7309af7e29
4 changed files with 273 additions and 32 deletions

View File

@ -40,7 +40,7 @@ class rom_base_array(bitcell_base_array):
self.place_ptx()
#self.route_horizontal_pins(insts=self.cell_inst.values(), layer=self.route_layer, name="S")
self.route_bitlines()
#self.route_bitlines()
#self.route_wordlines()
self.route_supplies()
@ -51,17 +51,26 @@ class rom_base_array(bitcell_base_array):
#def add_pins(self):
def add_boundary(self):
self.width = self.nmos.width * self.column_size
self.height = self.nmos.height * self.row_size
self.width = self.cell.width * self.column_size
self.height = self.cell.height * self.row_size
super().add_boundary()
def add_modules(self):
self.nmos = factory.create(module_type="ptx", tx_type="nmos", add_source_contact=self.route_layer,
add_drain_contact=self.route_layer)
temp = self.nmos.width
self.nmos.width = self.nmos.height + self.nmos.poly_extend_active
self.nmos.height = temp
# base cell, nmos tx that represents a 1
self.cell = factory.create(module_type="rom_base_cell")
# "dummy" cells represent 0
#dummy cell with no contacts
self.dummy_nc = factory.create(module_type="rom_dummy_cell")
#dummy cell with drain contact
self.dummy_dc = factory.create(module_type="rom_dummy_cell", drain_contact=True)
#dummy cell with source contact
self.dummy_sc = factory.create(module_type="rom_dummy_cell", source_contact=True)
#dummy cell with all contacts
self.dummy_ac = factory.create(module_type="rom_dummy_cell", source_contact=True, drain_contact=True)
def create_instances(self):
self.cell_inst = {}
self.cell_list = []
@ -75,11 +84,31 @@ class rom_base_array(bitcell_base_array):
if(self.data[row][col] == 1):
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.nmos, rotate=90)
mod=self.cell)
row_list.append(self.cell_inst[row, col])
self.connect_inst(self.get_bitcell_pins(row, col))
else: row_list.append(None)
self.connect_inst(["vdd", "gnd", "gnd"])
else:
if col < self.column_size - 1 and col > 0 and self.data[row][col + 1] == 1 and self.data[row][col - 1] == 1:
self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_ac)
elif col > 0 and self.data[row][col - 1] == 1:
self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_dc)
elif col < self.column_size - 1 and self.data[row][col + 1] == 1:
self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_sc)
else:
self.cell_inst[row, col]=self.add_inst(name=name, mod=self.dummy_nc)
self.connect_inst([])
row_list.append(self.cell_inst[row, col])
self.cell_list.append(row_list)
@ -94,34 +123,40 @@ class rom_base_array(bitcell_base_array):
def place_ptx(self):
self.cell_pos = {}
for col in range(self.column_size):
for row in range(self.row_size):
# rows are bitlines
for row in range(self.row_size):
# columns are word lines
for col in range(self.column_size):
#cell_x = (self.nmos.height + self.nmos.poly_extend_active) * col
#cell_y = (self.nmos.width + 2 * self.nmos.active_contact_to_gate + self.nmos.contact_width) * row
cell_x = self.nmos.width * col
cell_y = self.nmos.height * row
print(self.nmos.height + self.nmos.poly_extend_active)
cell_x = (self.cell.width) * col
cell_y = row * (self.cell.height)
self.cell_pos[row, col] = vector(cell_x, cell_y)
self.cell_inst[row, col].place(self.cell_pos[row, col])
#cell_x = self.cell.width * col
#cell_y = self.cell.height * row
#print(self.nmos.height + self.nmos.poly_extend_active)
if(self.data[row][col] == 1):
pass
self.cell_pos[row, col] = self.nmos.active_offset.scale(1, 0) \
+ vector(cell_x, cell_y)
self.cell_inst[row, col].place(self.cell_pos[row, col], rotate=90)
self.add_label("S_{}_{}".format(row,col), self.route_layer, self.cell_inst[row, col].get_pin("S").center())
self.add_label("D", self.route_layer, self.cell_inst[row, col].get_pin("D").center())
#self.add_label("S_{}_{}".format(row,col), self.route_layer, self.cell_inst[row, col].center())
#self.add_label("D", self.route_layer, self.cell_inst[row, col].center())
else:
#else:
#poly_offset = (self.nmos.contact_offset + vector(0.5 * self.nmos.active_contact.width + 0.5 * self.nmos.poly_width + self.nmos.active_contact_to_gate, 0)) + (0, cell_y)
poly_offset = (cell_x, cell_y)
#poly_offset = (cell_x, cell_y)
#print(cell_x,cell_y)
self.add_rect(layer="poly",
offset=poly_offset,
width=self.nmos.height + self.nmos.poly_extend_active,
height=self.nmos.poly_width
)
#self.add_rect(layer="poly",
# offset=poly_offset,
# width=self.nmos.height + self.nmos.poly_extend_active,
# height=self.nmos.poly_width
# )

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@ -0,0 +1,81 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import math
from .rom_dummy_cell import rom_dummy_cell
from base import design
from base import vector
from globals import OPTS
from sram_factory import factory
from tech import drc
class rom_base_cell(rom_dummy_cell):
def __init__(self, name="", cell_name=None):
super().__init__(name, cell_name)
#self.route_layer= route_layer
#self.create_netlist()
#self.create_layout()
def create_netlist(self):
print("using base cell netlist creation")
self.add_pins()
self.add_nmos()
self.create_nmos()
def create_layout(self):
self.setup_drc_offsets()
self.place_nmos()
self.add_boundary()
print(self.height)
print(self.width)
def add_pins(self):
pin_list = ["bl_h", "bl_l", "wl"]
dir_list = ["INOUT", "GROUND", "INPUT"]
self.add_pin_list(pin_list, dir_list)
def create_nmos(self):
self.cell_inst = self.add_inst( name=self.name,
mod=self.nmos,
rotate=90)
self.connect_inst(["bl_h", "wl", "bl_l", "gnd"])
def place_nmos(self):
poly_offset = vector(0.5 * self.nmos.active_contact.width + self.nmos.active_contact_to_gate,
self.nmos.poly_height)
nmos_offset = vector(- 0.5 * self.nmos.contact_width - self.active_enclose_contact, self.nmos.poly_extend_active)
# add rect of poly to account for offset from drc spacing
self.add_rect("poly", poly_offset, self.nmos.poly_width, self.poly_extend_active_spacing )
self.cell_inst.place(nmos_offset)
self.add_label("S", self.route_layer, self.cell_inst.get_pin("S").center())
self.add_label("D", self.route_layer, self.cell_inst.get_pin("D").center())

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@ -0,0 +1,125 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from base import design
from base import vector
from globals import OPTS
from sram_factory import factory
from tech import drc
class rom_dummy_cell(design):
def __init__(self, name="", cell_name=None, source_contact=False, drain_contact=False):
super().__init__(name, cell_name)
self.route_layer = "m1"
self.source_contact=source_contact
self.drain_contact=drain_contact
self.create_netlist()
self.create_layout()
def create_netlist(self):
#creates nmos for layout dimensions
self.add_nmos()
#set height and width such that the cell will tile perfectly by only ofsetting in the array by its width and height
def create_layout(self):
self.setup_drc_offsets()
self.add_boundary()
self.add_poly()
self.add_metal()
#poly_offset =
# vector(0.5 * self.nmos.active_contact.width + 0.5 * self.nmos.poly_width + self.nmos.active_contact_to_gate, 0)
#self.add_rect( layer="poly",
# offset=poly_offset,
# height=self.nmos.height + self.nmos.poly_extend_active,
# width=self.nmos.poly_width
# )
self.add_label("0,0", self.route_layer)
#self.add_wire( layers=self.route_layer)
#self.add_rect( layer=self.route_layer)
# Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules
def setup_drc_offsets(self):
#nmos contact to gate distance
self.contact_to_gate = 0.5 * (self.nmos.width - 2 * self.nmos.contact_width - self.nmos.poly_width - 2 * self.active_enclose_contact)
#height offset to account for active-to-active spacing between adjacent bitlines
self.poly_extend_active_spacing = abs( 2 * self.nmos.poly_extend_active - drc("active_to_active") )
#contact to contact distance, minimum cell width before drc offsets
self.base_width = self.nmos.width - 2 * self.active_enclose_contact - self.nmos.contact_width
#width offset to account for active-to-active spacing between cells on the same bitline
#this is calculated as a negative value
self.cell_diffusion_offset = ((self.base_width - 2 * self.active_enclose_contact - self.nmos.contact_width) - drc("active_to_active")) * 0.5
# width offset to account for poly-active spacing between base and dummy cells on the same bitline
self.poly_active_offset = 0.5 * (self.base_width - 2 * self.cell_diffusion_offset - (self.poly_width + 2 * self.active_enclose_contact + self.nmos.contact_width)) - self.poly_to_active
def add_boundary(self):
#cell height with offsets applied
self.height = self.nmos.height + self.poly_extend_active_spacing + 2 * self.nmos.poly_extend_active
# cell width with offsets applied, if the offsets are positive (greater than 0) they are not applied
self.width = self.base_width - min(self.cell_diffusion_offset, 0) - min(self.poly_active_offset, 0)
super().add_boundary()
def add_poly(self):
poly_x = 0.5 * self.nmos.contact_width + self.contact_to_gate
self.add_rect("poly", vector(poly_x, 0), self.poly_width, self.height)
def add_metal(self):
wire_x = min(self.cell_diffusion_offset, 0) + min(self.poly_active_offset, 0)
wire_y = 0.5 * (self.height - self.poly_extend_active_spacing)
wire_start = vector( wire_x, wire_y )
wire_end = vector(self.width, wire_y)
if self.route_layer == 'm1':
if self.drain_contact:
self.add_via_center(self.li_stack, [wire_x, wire_y])
if self.source_contact:
self.add_via_center(self.li_stack, [self.width, wire_y])
self.add_path(self.route_layer, [wire_start, wire_end])
def add_nmos(self):
#used only for layout constants
self.nmos = factory.create(module_type="ptx",
tx_type="nmos"
)

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@ -24,7 +24,7 @@ class rom_array_test(openram_test):
debug.info(2, "Testing 4x4 array for rom cell")
data = [[1, 1, 1, 1], [1, 1, 1, 1], [1, 0, 1, 1], [1, 1, 1, 0]]
data = [[1, 0, 0, 0], [0, 1, 1, 1], [1, 0, 1, 1], [1, 1, 0, 1]]
a = factory.create(module_type="rom_base_array", cols=4, rows=4, bitmap=data)
self.local_check(a)