Update versions of tools. Fix supply bug in predecode.

Makefile

@@ -3,9 +3,6 @@ include $(TOP_DIR)/openram.mk
 
 .DEFAULT_GOAL := install
 
-# Keep it locally if they didn't specify
-PDK_ROOT ?= $(TOP_DIR)
-
 # Skywater PDK SRAM library
 SRAM_LIB_DIR ?= $(PDK_ROOT)/sky130_fd_bd_sram
 SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git
@@ -15,8 +12,8 @@ SRAM_LIB_GIT_COMMIT ?= 95287ef89556505b2cdf17912c025cb74d9288a7
 # Open PDKs
 OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks
 OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git
-#OPEN_PDKS_GIT_COMMIT ?= 1.0.156
-OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608
+OPEN_PDKS_GIT_COMMIT ?= 1.0.311
+#OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608
 SKY130_PDK ?= $(PDK_ROOT)/sky130A
 
 # Skywater PDK

compiler/modules/hierarchical_predecode.py

@@ -416,4 +416,4 @@ class hierarchical_predecode(design.design):
                         else:
                             xoffset = self.inv_inst[0].lx() - self.bus_space
                         pin_pos = vector(xoffset, and_pin.cy())
-                        self.add_power_pin(n, pin_pos)
+                        self.add_power_pin(n, pin_pos, start_layer=and_pin.layer)

compiler/verify/magic.py

@@ -95,7 +95,8 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
     #f.write("gds polygon subcell true\n")
     f.write("gds warning default\n")
     # Flatten the transistors
-    f.write("gds flatglob *_?mos_m*\n")
+    # Bug in Netgen 1.5.194 when using this...
+    #f.write("gds flatglob *_?mos_m*\n")
     # These two options are temporarily disabled until Tim fixes a bug in magic related
     # to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
     # they appear to be disconnected.
@@ -123,7 +124,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
     # Hack to work around unit scales in SkyWater
     if OPTS.tech_name=="sky130":
         f.write(pre + "extract style ngspice(si)\n")
-    f.write(pre + "extract\n")
+    f.write(pre + "extract all\n")
     f.write(pre + "select top cell\n")
     f.write(pre + "feedback why\n")
     f.write('puts "Finished extract"\n')

docker/Dockerfile

@@ -111,8 +111,8 @@ RUN ./autogen.sh \
 RUN rm -rf /root/ngspice
 
 ### Netgen ###
-#ARG NETGEN_COMMIT=1.5.219
-ARG NETGEN_COMMIT=88d53fab15eb611cffc024eebf8743fae5cf8cb7
+#ARG NETGEN_COMMIT=1.5.195
+ARG NETGEN_COMMIT=1.5.221
 WORKDIR /root
 #RUN git clone https://github.com/RTimothyEdwards/netgen.git netgen
 RUN git clone git://opencircuitdesign.com/netgen netgen
@@ -129,7 +129,7 @@ RUN apt-get install --no-install-recommends -y iverilog
 ### Magic ###
 #ARG MAGIC_COMMIT=db4fa65bfc096e63954b37b188ea27b90ab31839
 #ARG MAGIC_COMMIT=8.3.274
-ARG MAGIC_COMMIT=8.3.211
+ARG MAGIC_COMMIT=8.3.309
 WORKDIR /root
 #RUN git clone https://github.com/RTimothyEdwards/magic.git magic
 RUN git clone git://opencircuitdesign.com/magic magic

openram.mk

@@ -1,11 +1,18 @@
 OPENRAM_HOME := $(abspath $(TOP_DIR)/compiler)
 OPENRAM_TECH := $(abspath $(TOP_DIR)/technology)
 OPENRAM_COMPILER := $(OPENRAM_HOME)/openram.py
+
+PDK_ROOT = $(TOP_DIR)
+
 ifeq (,$(wildcard $(OPENRAM_COMPILER)))
 $(error Did not find '$(OPENRAM_COMPILER)' in '$(OPENRAM_HOME)' (from $$OPENRAM_HOME))
 endif
 export OPENRAM_HOME
 export OPENRAM_TECH
+export PDK_ROOT
+#$(info Using OPENRAM_HOME=$(OPENRAM_HOME))
+#$(info Using OPENRAM_TECH=$(OPENRAM_TECH))
+#$(info Using PDK_ROOT=$(PDK_ROOT))
 
 UID = $(shell id -u)
 GID = $(shell id -g)