mirror of https://github.com/VLSIDA/OpenRAM.git
Fix power ring routing boundary bug.
This commit is contained in:
mrg
parent
7e7670581c
commit
01a73b31e1
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@ -1322,7 +1322,7 @@ class layout():
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self.bbox = [self.bounding_box.ll(), self.bounding_box.ur()]
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def get_bbox(self, side="all", big_margin=0, little_margin=0):
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def get_bbox(self, side="all", margin=0):
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"""
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Get the bounding box from the GDS
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"""
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@ -1349,27 +1349,18 @@ class layout():
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ll_offset = vector(0, 0)
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ur_offset = vector(0, 0)
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if side in ["ring", "top", "all"]:
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ur_offset += vector(0, big_margin)
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else:
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ur_offset += vector(0, little_margin)
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ur_offset += vector(0, margin)
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if side in ["ring", "bottom", "all"]:
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ll_offset += vector(0, big_margin)
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else:
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ll_offset += vector(0, little_margin)
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ll_offset += vector(0, margin)
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if side in ["ring", "left", "all"]:
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ll_offset += vector(big_margin, 0)
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else:
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ll_offset += vector(little_margin, 0)
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ll_offset += vector(margin, 0)
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if side in ["ring", "right", "all"]:
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ur_offset += vector(big_margin, 0)
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else:
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ur_offset += vector(little_margin, 0)
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ur_offset += vector(margin, 0)
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bbox = (ll - ll_offset, ur + ur_offset)
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size = ur - ll
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debug.info(1, "Size: {0} x {1} with perimeter big margin {2} little margin {3}".format(size.x,
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debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x,
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size.y,
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big_margin,
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little_margin))
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margin))
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return bbox
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@ -177,15 +177,18 @@ class delay_chain(design.design):
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# The routing to connect the loads is over the first and last cells
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# We have an even number of drivers and must only do every other
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# supply rail
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if OPTS.experimental_power:
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self.route_horizontal_pins("vdd")
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self.route_horizontal_pins("gnd")
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else:
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for inst in self.driver_inst_list:
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load_list = self.load_inst_map[inst]
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for pin_name in ["vdd", "gnd"]:
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pin = load_list[0].get_pin(pin_name)
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self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
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for inst in self.driver_inst_list:
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load_list = self.load_inst_map[inst]
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for pin_name in ["vdd", "gnd"]:
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pin = load_list[0].get_pin(pin_name)
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self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
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pin = load_list[-2].get_pin(pin_name)
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self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
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pin = load_list[-2].get_pin(pin_name)
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self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
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def add_layout_pins(self):
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@ -78,7 +78,7 @@ class wordline_driver_array(design.design):
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"""
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# Experiment with power straps
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if OPTS.experimental_power:
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if OPTS.tech_name=="sky130" or OPTS.experimental_power:
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if layer_props.wordline_driver.vertical_supply:
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self.route_vertical_pins("vdd", insts=self.wld_inst)
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self.route_vertical_pins("gnd", insts=self.wld_inst)
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@ -68,6 +68,16 @@ class grid:
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self.add_map(n)
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return self.map[n].blocked
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def is_inside(self, n):
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if not isinstance(n, vector3d):
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for item in n:
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if self.is_inside(item):
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return True
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else:
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return False
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else:
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return n.x >= self.ll.x and n.x <= self.ur.x and n.y >= self.ll.y and n.y <= self.ur.y
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def set_path(self, n, value=True):
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if isinstance(n, (list, tuple, set, frozenset)):
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for item in n:
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@ -128,7 +138,7 @@ class grid:
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"""
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Side specifies which side.
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Layer specifies horizontal (0) or vertical (1)
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Width specifies how wide the perimter "stripe" should be.
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Width specifies how wide the perimeter "stripe" should be.
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Works from the inside out from the bbox (ll, ur)
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"""
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if "ring" in side:
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@ -92,12 +92,19 @@ class router(router_tech):
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def get_bbox(self):
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return self.bbox
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def create_routing_grid(self, router_type):
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def create_routing_grid(self, router_type=None):
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"""
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Create a sprase routing grid with A* expansion functions.
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Create (or recreate) a sprase routing grid with A* expansion functions.
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"""
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debug.check(router_type or hasattr(self, "router_type"), "Must specify a routing grid type.")
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self.init_bbox(self.bbox, self.margin)
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self.rg = router_type(self.ll, self.ur, self.track_width)
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if router_type:
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self.router_type = router_type
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self.rg = router_type(self.ll, self.ur, self.track_width)
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else:
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self.rg = self.router_type(self.ll, self.ur, self.track_width)
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def clear_pins(self):
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"""
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@ -927,40 +934,34 @@ class router(router_tech):
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def add_ring_supply_pin(self, name, width=3, space=2):
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"""
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Adds a ring supply pin that goes inside the given bbox.
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Adds a ring supply pin that goes outside the given bbox.
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"""
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pg = pin_group(name, [], self)
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# Offset two spaces inside and one between the rings
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# Units are in routing grids
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if name == "gnd":
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offset = width + 2 * space
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else:
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offset = space
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# LEFT
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left_grids = set(self.rg.get_perimeter_list(side="left_ring",
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width=width,
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margin=self.margin,
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offset=offset,
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offset=space,
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layers=[1]))
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# RIGHT
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right_grids = set(self.rg.get_perimeter_list(side="right_ring",
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width=width,
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margin=self.margin,
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offset=offset,
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offset=space,
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layers=[1]))
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# TOP
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top_grids = set(self.rg.get_perimeter_list(side="top_ring",
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width=width,
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margin=self.margin,
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offset=offset,
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offset=space,
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layers=[0]))
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# BOTTOM
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bottom_grids = set(self.rg.get_perimeter_list(side="bottom_ring",
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width=width,
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margin=self.margin,
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offset=offset,
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offset=space,
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layers=[0]))
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horizontal_layer_grids = left_grids | right_grids
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@ -972,6 +973,7 @@ class router(router_tech):
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# Add vias in the overlap points
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horizontal_corner_grids = vertical_layer_grids & horizontal_layer_grids
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corners = []
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for g in horizontal_corner_grids:
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self.add_via(g)
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@ -984,6 +986,15 @@ class router(router_tech):
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self.pin_groups[name].append(pg)
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self.new_pins[name] = pg.pins
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# Update the bbox so that it now includes the new pins
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for p in pg.pins:
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if p.lx() < self.ll.x or p.by() < self.ll.y:
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self.ll = p.ll()
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if p.rx() > self.ur.x or p.uy() > self.ur.y:
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self.ur = p.ur()
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self.bbox = (self.ll, self.ur)
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self.create_routing_grid()
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def get_new_pins(self, name):
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return self.new_pins[name]
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@ -1274,11 +1285,18 @@ class router(router_tech):
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"""
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debug.info(2, "Adding router info")
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show_bbox = False
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show_blockages = False
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show_blockage_grids = False
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show_enclosures = False
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show_all_grids = True
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if show_bbox:
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self.cell.add_rect(layer="text",
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offset=vector(self.ll.x, self.ll.y),
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width=self.ur.x - self.ll.x,
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height=self.ur.y - self.ll.y)
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if show_all_grids:
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for g in self.rg.map:
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self.annotate_grid(g)
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@ -63,7 +63,7 @@ class signal_escape_router(router):
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print_time("Maze routing pins",datetime.now(), start_time, 3)
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# self.write_debug_gds("final_escape_router.gds",False)
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#self.write_debug_gds("final_escape_router.gds",False)
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return True
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@ -119,10 +119,11 @@ class signal_grid(grid):
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# Expand all directions.
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neighbors = curpath.expand_dirs()
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# Filter the out of region ones
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# Filter the blocked ones
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unblocked_neighbors = [x for x in neighbors if not self.is_blocked(x)]
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valid_neighbors = [x for x in neighbors if self.is_inside(x) and not self.is_blocked(x)]
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return unblocked_neighbors
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return valid_neighbors
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def hpwl(self, src, dest):
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"""
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@ -43,6 +43,7 @@ class supply_tree_router(router):
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bbox=bbox,
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route_track_width=self.route_track_width)
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def route(self, vdd_name="vdd", gnd_name="gnd"):
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"""
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Route the two nets in a single layer.
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@ -75,6 +76,9 @@ class supply_tree_router(router):
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self.add_ring_supply_pin(self.vdd_name)
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self.add_ring_supply_pin(self.gnd_name)
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#self.write_debug_gds("initial_tree_router.gds",False)
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#breakpoint()
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# Route the supply pins to the supply rails
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# Route vdd first since we want it to be shorter
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start_time = datetime.now()
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@ -82,8 +86,6 @@ class supply_tree_router(router):
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self.route_pins(gnd_name)
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print_time("Maze routing supplies", datetime.now(), start_time, 3)
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# self.write_debug_gds("final_tree_router.gds",False)
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# Did we route everything??
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if not self.check_all_routed(vdd_name):
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return False
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@ -144,15 +146,15 @@ class supply_tree_router(router):
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# Route MST components
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for index, (src, dest) in enumerate(connections):
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if not (index % 100):
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if not (index % 25):
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debug.info(1, "{0} supply segments routed, {1} remaining.".format(index, len(connections) - index))
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self.route_signal(pin_name, src, dest)
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# if pin_name == "gnd":
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# print("\nSRC {}: ".format(src) + str(self.pin_groups[pin_name][src].grids) + str(self.pin_groups[pin_name][src].blockages))
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# print("DST {}: ".format(dest) + str(self.pin_groups[pin_name][dest].grids) + str(self.pin_groups[pin_name][dest].blockages))
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# self.write_debug_gds("post_{0}_{1}.gds".format(src, dest), False)
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if False and pin_name == "gnd":
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print("\nSRC {}: ".format(src) + str(self.pin_groups[pin_name][src].grids) + str(self.pin_groups[pin_name][src].blockages))
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print("DST {}: ".format(dest) + str(self.pin_groups[pin_name][dest].grids) + str(self.pin_groups[pin_name][dest].blockages))
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self.write_debug_gds("post_{0}_{1}.gds".format(src, dest), False)
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#self.write_debug_gds("final.gds", True)
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#self.write_debug_gds("final_tree_router_{}.gds".format(pin_name), False)
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#return
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def route_signal(self, pin_name, src_idx, dest_idx):
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@ -161,7 +163,7 @@ class supply_tree_router(router):
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# Second pass, clear prior pin blockages so that you can route over other metal
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# of the same supply. Otherwise, this can create a lot of circular routes due to accidental overlaps.
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for unblock_routes in [False, True]:
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for detour_scale in [5 * pow(2, x) for x in range(5)]:
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for detour_scale in [2 * pow(2, x) for x in range(5)]:
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debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale))
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# Clear everything in the routing grid.
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@ -187,6 +189,8 @@ class supply_tree_router(router):
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# Actually run the A* router
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if self.run_router(detour_scale=detour_scale):
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return
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if detour_scale > 2:
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self.write_debug_gds("route_{0}_{1}_d{2}.gds".format(src_idx, dest_idx, detour_scale), False)
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self.write_debug_gds("debug_route.gds", True)
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@ -336,31 +336,27 @@ class sram_1bank(sram_base):
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# Some technologies have an isolation
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self.add_dnwell(inflate=2.5)
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# Route the supplies together and/or to the ring/stripes.
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# This is done with the original bbox since the escape routes need to
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# be outside of the ring for OpenLane
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rt = router_tech(self.supply_stack, 1)
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init_bbox = self.get_bbox(side="ring",
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margin=rt.track_width)
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# We need the initial bbox for the supply rings later
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# because the perimeter pins will change the bbox
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# Route the pins to the perimeter
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pre_bbox = None
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if OPTS.perimeter_pins:
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rt = router_tech(self.supply_stack, 1)
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if OPTS.supply_pin_type in ["ring", "left", "right", "top", "bottom"]:
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big_margin = 12 * rt.track_width
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little_margin = 2 * rt.track_width
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else:
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big_margin = 6 * rt.track_width
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little_margin = 0
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pre_bbox = self.get_bbox(side="ring",
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big_margin=rt.track_width)
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bbox = self.get_bbox(side=OPTS.supply_pin_type,
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big_margin=big_margin,
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little_margin=little_margin)
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# We now route the escape routes far enough out so that they will
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# reach past the power ring or stripes on the sides
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# The power rings are 4 tracks wide with 2 tracks spacing, so space it
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# 11 tracks out
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bbox = self.get_bbox(side="ring",
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margin=11*rt.track_width)
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self.route_escape_pins(bbox)
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# Route the supplies first since the MST is not blockage aware
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# and signals can route to anywhere on sides (it is flexible)
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self.route_supplies(pre_bbox)
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self.route_supplies(init_bbox)
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def route_dffs(self, add_routes=True):
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@ -243,6 +243,7 @@ class sram_base(design, verilog, lef):
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for inst in self.insts:
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self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name])
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# Pick the router type
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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@ -250,6 +251,7 @@ class sram_base(design, verilog, lef):
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from supply_grid_router import supply_grid_router as router
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else:
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from supply_tree_router import supply_tree_router as router
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rtr=router(layers=self.supply_stack,
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design=self,
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bbox=bbox,
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@ -257,6 +259,8 @@ class sram_base(design, verilog, lef):
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rtr.route()
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# This removes the original pre-supply routing pins and replaces them
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# with the ring or peripheral power pins
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if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]:
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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