mirror of https://github.com/VLSIDA/OpenRAM.git
Move delay line supply strap for pin access.
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@ -172,9 +172,11 @@ class delay_chain(design.design):
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self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()])
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def route_supplies(self):
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self.route_vertical_pins("vdd", self.driver_inst_list, xside="lx")
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# These pins get routed in one cell from the left/right
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# because the input signal gets routed on M3 and can interfere with the delay input.
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self.route_vertical_pins("vdd", self.driver_inst_list, xside="rx")
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right_load_insts = [self.load_inst_map[x][-1] for x in self.driver_inst_list]
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self.route_vertical_pins("gnd", right_load_insts, xside="rx")
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self.route_vertical_pins("gnd", right_load_insts, xside="lx")
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def add_layout_pins(self):
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