mirror of https://github.com/VLSIDA/OpenRAM.git
Fix offsets for local bitcell arrays.
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357f967a93
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@ -159,18 +159,20 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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def place(self):
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""" Place the bitcelll array to the right of the wl driver. """
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# FIXME: Replace this with a tech specific paramter
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# FIXME: Replace this with a tech specific parameter
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driver_to_array_spacing = 3 * self.m3_pitch
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self.wl_insts[0].place(vector(0,
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self.bitcell_array.get_replica_bottom() + self.cell.height))
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wl_offset = vector(0, self.bitcell_array.get_replica_bottom())
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self.wl_insts[0].place(wl_offset)
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self.bitcell_array_inst.place(vector(self.wl_insts[0].rx() + driver_to_array_spacing,
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0))
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bitcell_array_offset = vector(self.wl_insts[0].rx() + driver_to_array_spacing, 0)
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self.bitcell_array_inst.place(bitcell_array_offset)
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if len(self.all_ports) > 1:
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self.wl_insts[1].place(vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
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self.bitcell_array.get_replica_top() + self.cell.height),
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wl_offset = vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
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self.bitcell_array.get_replica_bottom() + self.wl_array.height + self.cell.height)
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self.wl_insts[1].place(wl_offset,
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mirror="XY")
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self.height = self.bitcell_array.height
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@ -353,28 +353,36 @@ class replica_bitcell_array(bitcell_base_array):
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self.DRC_LVS()
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def get_main_array_top(self):
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""" Return the top of the main bitcell array. """
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return self.bitcell_array_inst.uy()
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def get_main_array_bottom(self):
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""" Return the bottom of the main bitcell array. """
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return self.bitcell_array_inst.by()
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def get_main_array_left(self):
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""" Return the left of the main bitcell array. """
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return self.bitcell_array_inst.lx()
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def get_main_array_right(self):
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""" Return the right of the main bitcell array. """
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return self.bitcell_array_inst.rx()
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def get_replica_top(self):
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return max([x.uy() for x in self.replica_col_insts if x] + [self.get_main_array_top()])
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""" Return the top of all replica columns. """
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return self.dummy_row_insts[0].by()
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def get_replica_bottom(self):
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return min([x.by() for x in self.replica_col_insts if x] + [self.get_main_array_bottom()])
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""" Return the bottom of all replica columns. """
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return self.dummy_row_insts[0].uy()
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def get_replica_left(self):
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return min([x.lx() for x in self.replica_col_insts if x] + [self.get_main_array_left()])
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""" Return the left of all replica columns. """
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return self.dummy_col_insts[0].rx()
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def get_replica_right(self):
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return min([x.rx() for x in self.replica_col_insts if x] + [self.get_main_array_right()])
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""" Return the right of all replica columns. """
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return self.dummy_col_insts[1].rx()
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def get_column_offsets(self):
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"""
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@ -44,7 +44,10 @@ class wordline_buffer_array(design.design):
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self.place_drivers()
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self.route_layout()
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self.route_supplies()
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self.offset_all_coordinates()
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# Don't offset these because some cells use standard cell style drivers
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#self.offset_all_coordinates()
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self.add_boundary()
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self.DRC_LVS()
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@ -71,31 +74,11 @@ class wordline_buffer_array(design.design):
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are must-connects next level up.
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"""
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if layer_props.wordline_driver.vertical_supply:
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for name in ["vdd", "gnd"]:
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supply_pins = self.wld_inst[0].get_pins(name)
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for pin in supply_pins:
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self.add_layout_pin_segment_center(text=name,
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layer=pin.layer,
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start=pin.bc(),
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end=vector(pin.cx(), self.height))
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self.route_vertical_pins("vdd", self.wld_inst)
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self.route_vertical_pins("gnd", self.wld_inst)
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else:
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# Find the x offsets for where the vias/pins should be placed
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xoffset_list = [self.wld_inst[0].rx()]
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for num in range(self.rows):
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# this will result in duplicate polygons for rails, but who cares
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# use the inverter offset even though it will be the and's too
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(gate_offset, y_dir) = self.get_gate_offset(0,
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self.wl_driver.height,
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num)
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# Route both supplies
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for name in ["vdd", "gnd"]:
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supply_pin = self.wld_inst[num].get_pin(name)
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# Add pins in two locations
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for xoffset in xoffset_list:
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pin_pos = vector(xoffset, supply_pin.cy())
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self.copy_power_pin(supply_pin, loc=pin_pos)
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self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
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self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
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def create_drivers(self):
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self.wld_inst = []
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