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array generation and bitline routing with array module

This commit is contained in:
Jacob Walker 2022-08-04 12:47:17 -07:00
parent 4db5c3be26
commit d7ac26a053
2 changed files with 123 additions and 41 deletions
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160
compiler/modules/rom_base_array.py
View File

@ -17,8 +17,10 @@ class rom_base_array(bitcell_base_array):
def __init__(self, rows, cols, bitmap, name="", column_offset=0):
super().__init__(name=name, rows=rows, cols=cols, column_offset=column_offset)
#TODO: data is input in col-major order for ease of parsing, create a function to convert a row-major input to col-major
self.data = bitmap
self.route_layer = 'm1'
self.create_all_bitline_names()
self.create_all_wordline_names()
self.create_netlist()
@ -29,15 +31,21 @@ class rom_base_array(bitcell_base_array):
def create_netlist(self):
self.add_modules()
self.add_pins()
self.create_instances()
def create_layout(self):
#self.add_layout_pins()
self.place_ptx()
#self.route_horizontal_pins(insts=self.cell_inst.values(), layer=self.route_layer, name="S")
self.route_bitlines()
#self.route_wordlines()
self.route_supplies()
#self.add_boundary()
self.add_boundary()
#self.DRC_LVS()
@ -49,42 +57,30 @@ class rom_base_array(bitcell_base_array):
def add_modules(self):
self.nmos = factory.create(module_type="ptx", tx_type="nmos")
self.nmos = factory.create(module_type="ptx", tx_type="nmos", add_source_contact=self.route_layer,
add_drain_contact=self.route_layer)
temp = self.nmos.width
self.nmos.width = self.nmos.height + self.nmos.poly_extend_active
self.nmos.height = temp
def create_instances(self):
self.cell_inst = {}
self.cell_list = []
self.current_row = 0
for col in range(self.column_size):
for row in range(self.row_size):
for row in range(self.row_size):
row_list = []
for col in range(self.column_size):
name = "bit_r{0}_c{1}".format(row, col)
if(self.data[col][row] == 1):
if(self.data[row][col] == 1):
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.nmos)
mod=self.nmos, rotate=90)
row_list.append(self.cell_inst[row, col])
self.connect_inst(self.get_bitcell_pins(row, col))
# If it is a "core" cell, it could be trimmed for sim time
#if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
# self.trim_insts.add(name)
def place_ptx(self):
self.cell_pos = {}
for col in range(self.column_size):
for row in range(self.row_size):
if(self.data[col][row] == 1):
cell_x = (self.nmos.width + 2 * self.nmos.active_contact_to_gate + self.nmos.contact_width) * col
cell_y = (self.nmos.height + self.nmos.poly_extend_active) * row
self.cell_pos[row, col] = self.nmos.active_offset.scale(1, 0) \
+ vector(cell_x, cell_y)
self.cell_inst[row, col].place(self.cell_pos[row, col])
else: row_list.append(None)
self.cell_list.append(row_list)
@ -96,7 +92,95 @@ class rom_base_array(bitcell_base_array):
self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
def place_ptx(self):
self.cell_pos = {}
for col in range(self.column_size):
for row in range(self.row_size):
#cell_x = (self.nmos.height + self.nmos.poly_extend_active) * col
#cell_y = (self.nmos.width + 2 * self.nmos.active_contact_to_gate + self.nmos.contact_width) * row
cell_x = self.nmos.width * col
cell_y = self.nmos.height * row
print(self.nmos.height + self.nmos.poly_extend_active)
if(self.data[row][col] == 1):
self.cell_pos[row, col] = self.nmos.active_offset.scale(1, 0) \
+ vector(cell_x, cell_y)
self.cell_inst[row, col].place(self.cell_pos[row, col], rotate=90)
self.add_label("S_{}_{}".format(row,col), self.route_layer, self.cell_inst[row, col].get_pin("S").center())
self.add_label("D", self.route_layer, self.cell_inst[row, col].get_pin("D").center())
else:
#poly_offset = (self.nmos.contact_offset + vector(0.5 * self.nmos.active_contact.width + 0.5 * self.nmos.poly_width + self.nmos.active_contact_to_gate, 0)) + (0, cell_y)
poly_offset = (cell_x, cell_y)
#print(cell_x,cell_y)
self.add_rect(layer="poly",
offset=poly_offset,
width=self.nmos.height + self.nmos.poly_extend_active,
height=self.nmos.poly_width
)
def route_bitlines(self):
#get first nmos in col
#connect to main bitline wire
#get next nmos in col
#route source to drain
#loop
for col in range(self.column_size):
for row in range(self.row_size ):
#nmos at this position and another nmos further down
if self.data[row][col] == 1 :
next_row = self.get_next_cell_in_bl(row, col)
if next_row != -1:
drain_pin = self.cell_inst[row, col].get_pin("D")
source_pin = self.cell_inst[next_row, col].get_pin("S")
source_pos = source_pin.bc()
drain_pos = drain_pin.bc()
self.add_path(self.route_layer, [drain_pos, source_pos])
def get_next_cell_in_bl(self, row_start, col):
for row in range(row_start + 1, self.row_size):
if self.data[row][col] == 1:
return row
return -1
def get_current_bl_interconnect(self, col):
"""Get interconnect net for bitline(col) currently being connected """
return "bli_{0}_{1}".format(self.current_row, col)
def create_next_bl_interconnect(self, row, col):
"""create a new net name for a bitline interconnect"""
self.current_row = row
return "bli_{0}_{1}".format(row, col)
def get_bitcell_pins(self, row, col):
"""
return the correct nets to attack nmos/cell drain, gate, source, body pins to
"""
bitcell_pins = []
#drain pin
@ -111,21 +195,19 @@ class rom_base_array(bitcell_base_array):
#source pin
if 1 not in self.data[col][row + 1:]:
"""If there is another bitcell to be placed below the current cell, """
if self.get_next_cell_in_bl(row, col) == -1:
bitcell_pins.append("gnd")
else:
"""create another interconnect net"""
bitcell_pins.append(self.create_next_bl_interconnect(row, col))
#body pin
bitcell_pins.append("gnd")
return bitcell_pins
def create_next_bl_interconnect(self, row, col):
self.current_row = row
return "bli_{0}_{1}".format(row, col)
def get_current_bl_interconnect(self, col):
return "bli_{0}_{1}".format(self.current_row, col)

4
compiler/tests/05_rom_array_test.py
View File

@ -24,7 +24,7 @@ class rom_array_test(openram_test):
debug.info(2, "Testing 4x4 array for rom cell")
data = [[1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1]]
data = [[1, 1, 1, 1], [1, 1, 1, 1], [1, 0, 1, 1], [1, 1, 1, 0]]
a = factory.create(module_type="rom_base_array", cols=4, rows=4, bitmap=data)
self.local_check(a)
@ -36,4 +36,4 @@ if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
unittest.main(testRunner=debugTestRunner())