mirror of https://github.com/VLSIDA/OpenRAM.git
Add missing via in dff array
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@ -119,12 +119,12 @@ class dff_array(design.design):
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# Add connections every 4 cells
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for col in range(0, self.columns, 4):
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vdd_pin=self.dff_insts[0, col].get_pin("vdd")
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self.add_power_pin("vdd", vdd_pin.lc())
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self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer)
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# Add connections every 4 cells
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for col in range(0, self.columns, 4):
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gnd_pin=self.dff_insts[0, col].get_pin("gnd")
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self.add_power_pin("gnd", gnd_pin.rc())
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self.add_power_pin("gnd", gnd_pin.rc(), start_layer=vdd_pin.layer)
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def add_layout_pins(self):
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for row in range(self.rows):
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