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Add some vertical/horizontal pins for sky130 only

This commit is contained in:
mrg 2022-03-16 07:58:29 -07:00
parent 8979612cca
commit 7e7670581c
4 changed files with 59 additions and 48 deletions
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76
compiler/base/hierarchy_layout.py
View File

@ -449,12 +449,19 @@ class layout():
bins[x] = [(inst,pin)]
for x, v in bins.items():
# Not enough to route a pin
# Not enough to route a pin, so just copy them
if len(v) < 2:
debug.warning("Copying pins instead of connecting with pin.")
for inst,pin in v:
self.add_layout_pin(pin.name,
pin.layer,
pin.ll(),
pin.width(),
pin.height())
continue
bot_y = min([inst.by() for (inst,pin) in v])
top_y = max([inst.uy() for (inst,pin) in v])
bot_y = min([pin.by() for (inst,pin) in v])
top_y = max([pin.uy() for (inst,pin) in v])
last_via = None
for inst,pin in v:
@ -477,16 +484,21 @@ class layout():
top_pos = vector(x, top_y)
bot_pos = vector(x, bot_y)
rect = self.add_layout_pin_rect_center(text=name,
layer=pin_layer,
offset=top_pos)
# self.add_layout_pin_rect_center(text=name,
# layer=pin_layer,
# offset=bot_pos)
self.add_segment_center(layer=pin_layer,
start=vector(rect.cx(), bot_pos.y),
end=rect.bc(),
width=via_width)
# top_rect = self.add_layout_pin_rect_center(text=name,
# layer=pin_layer,
# offset=top_pos)
#bot_rect = self.add_layout_pin_rect_center(text=name,
# layer=pin_layer,
# offset=bot_pos)
# self.add_segment_center(layer=pin_layer,
# start=vector(top_rect.cx(), bot_pos.y),
# end=top_rect.bc(),
# width=via_width)
self.add_layout_pin_segment_center(text=name,
layer=pin_layer,
start=top_pos,
end=bot_pos,
width=via_width)
@ -514,12 +526,18 @@ class layout():
# Filter the small bins
for y, v in bins.items():
# Not enough to route a pin
if len(v) < 2:
debug.warning("Copying pins instead of connecting with pin.")
for inst,pin in v:
self.add_layout_pin(pin.name,
pin.layer,
pin.ll(),
pin.width(),
pin.height())
continue
left_x = min([inst.lx() for (inst,pin) in v])
right_x = max([inst.rx() for (inst,pin) in v])
left_x = min([pin.lx() for (inst,pin) in v])
right_x = max([pin.rx() for (inst,pin) in v])
last_via = None
for inst,pin in v:
@ -543,19 +561,25 @@ class layout():
left_pos = vector(left_x, y)
right_pos = vector(right_x, y)
rect = self.add_layout_pin_rect_center(text=name,
layer=pin_layer,
offset=left_pos)
# self.add_layout_pin_rect_center(text=name,
# layer=pin_layer,
# offset=right_pos)
# left_rect = self.add_layout_pin_rect_center(text=name,
# layer=pin_layer,
# offset=left_pos)
#right_rect = self.add_layout_pin_rect_center(text=name,
# layer=pin_layer,
# offset=right_pos)
# This is made to not overlap with the pin above
# so that the power router will only select a small pin.
# Otherwise it adds big blockages over the rails.
self.add_segment_center(layer=pin_layer,
start=rect.rc(),
end=vector(right_pos.x, rect.cy()),
width=via_height)
# self.add_segment_center(layer=pin_layer,
# start=left_rect.rc(),
# end=vector(right_pos.x, left_rect.cy()),
# width=via_height)
self.add_layout_pin_segment_center(text=name,
layer=pin_layer,
start=left_pos,
end=right_pos,
width=via_height)
def add_layout_pin_segment_center(self, text, layer, start, end, width=None):

2
compiler/modules/hierarchical_decoder.py
View File

@ -596,7 +596,7 @@ class hierarchical_decoder(design.design):
"""
# This is an experiment with power rails
if OPTS.experimental_power:
if OPTS.tech_name=="sky130" or OPTS.experimental_power:
if layer_props.hierarchical_decoder.vertical_supply:
pre_insts = self.pre2x4_inst + self.pre3x8_inst + self.pre4x16_inst
self.route_vertical_pins("vdd", insts=pre_insts, yside="by")

2
compiler/modules/precharge_array.py
View File

@ -95,7 +95,7 @@ class precharge_array(design.design):
self.copy_layout_pin(inst, "br", "br_{0}".format(i))
def route_supplies(self):
if OPTS.experimental_power:
if OPTS.tech_name=="sky130" or OPTS.experimental_power:
self.route_horizontal_pins("vdd")
else:
for inst in self.local_insts:

27
compiler/modules/replica_bitcell_array.py
View File

@ -458,27 +458,14 @@ class replica_bitcell_array(bitcell_base_array):
width=pin.width(),
height=self.height)
# vdd/gnd are only connected in the perimeter cells
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
supply_insts = self.dummy_col_insts + self.dummy_row_insts
if OPTS.experimental_power:
for pin_name in self.supplies:
#self.route_vertical_pins(name=pin_name, insts=supply_insts)
self.route_horizontal_pins(name=pin_name, insts=supply_insts)
#self.route_vertical_pins(name=pin_name, insts=self.replica_col_insts)
#self.route_horizontal_pins(name=pin_name, insts=self.replica_col_insts)
for inst in supply_insts:
pin_list = inst.get_pins(pin_name)
for pin in pin_list:
self.copy_power_pin(pin)
for inst in self.replica_col_insts:
if inst:
self.copy_layout_pin(inst, pin_name)
if OPTS.tech_name=="sky130" or OPTS.experimental_power:
self.route_vertical_pins(name="gnd", insts=self.replica_col_insts)
self.route_horizontal_pins(name="vdd", insts=self.dummy_row_insts)
else:
# vdd/gnd are only connected in the perimeter cells
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
supply_insts = self.dummy_col_insts + self.dummy_row_insts
for pin_name in self.supplies:
for inst in supply_insts:
pin_list = inst.get_pins(pin_name)