mirror of https://github.com/VLSIDA/OpenRAM.git
Start dff array supplies on first rather than second bit.
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@ -117,12 +117,12 @@ class dff_array(design.design):
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else:
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# Add connections every 4 cells
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for col in range(1, self.columns, 4):
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for col in range(0, self.columns, 4):
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vdd_pin=self.dff_insts[0, col].get_pin("vdd")
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self.add_power_pin("vdd", vdd_pin.lc())
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# Add connections every 4 cells
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for col in range(1, self.columns, 4):
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for col in range(0, self.columns, 4):
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gnd_pin=self.dff_insts[0, col].get_pin("gnd")
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self.add_power_pin("gnd", gnd_pin.rc())
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