mirror of https://github.com/VLSIDA/OpenRAM.git
passing drc/lvs on 4x4 rom array
This commit is contained in:
Jacob Walker
parent
a3e271f6fb
commit
aea3c0ad01
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@ -0,0 +1,39 @@
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from base import design
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from base import vector
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from sram_factory import factory
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class rom_array_gnd_tap(design):
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def __init__(self, name, length, cell_name=None, prop=None):
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super().__init__(name, cell_name, prop)
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self.length = length
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self.create_layout()
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def create_layout(self):
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self.add_cell()
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self.add_boundary()
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self.place_gnd_rail()
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def add_boundary(self):
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self.height = self.dummy.height
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self.width = self.dummy.width
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super().add_boundary()
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def add_cell(self):
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self.dummy = factory.create(module_type="rom_dummy_cell")
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def place_gnd_rail(self):
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rail_start = vector(-self.dummy.width / 2 ,0)
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rail_end = vector(self.dummy.width * self.length, 0)
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self.add_layout_pin_rect_ends( name="gnd",
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layer="m1",
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start=rail_start,
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end=rail_end)
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@ -15,12 +15,13 @@ from sram_factory import factory
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class rom_base_array(bitcell_base_array):
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def __init__(self, rows, cols, bitmap, name="", column_offset=0):
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def __init__(self, rows, cols, strap_spacing, bitmap, name="", column_offset=0):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=column_offset)
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#TODO: data is input in col-major order for ease of parsing, create a function to convert a row-major input to col-major
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self.data = bitmap
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self.route_layer = 'm1'
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self.strap_spacing = strap_spacing
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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@ -33,22 +34,20 @@ class rom_base_array(bitcell_base_array):
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self.add_pins()
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self.create_instances()
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self.create_taps()
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def create_layout(self):
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#self.add_layout_pins()
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self.place_ptx()
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self.place_tap(self.column_size)
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self.place_tap(0)
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self.place_taps()
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self.place_rails()
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#self.route_horizo ntal_pins(insts=self.cell_inst.values(), layer=self.route_layer, name="S")
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#self.route_bitlines()
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#self.route_wordlines()
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self.route_supplies()
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self.add_boundary()
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#self.DRC_LVS()
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#def add_pins(self):
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def add_boundary(self):
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@ -58,67 +57,103 @@ class rom_base_array(bitcell_base_array):
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def add_modules(self):
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# base cell, nmos tx that represents a 1
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# dummy cell, # "dummy" cells represent 0
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self.dummy = factory.create(module_type="rom_dummy_cell", route_layer=self.route_layer)
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# "dummy" cells represent 0
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#dummy cell with no contacts
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self.cell_nc = factory.create(module_type="rom_base_cell")
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#dummy cell with drain contact
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self.cell_dc = factory.create(module_type="rom_base_cell", add_drain_contact=self.route_layer)
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#dummy cell with source contact
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self.cell_sc = factory.create(module_type="rom_base_cell", add_source_contact=self.route_layer)
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#dummy cell with all contacts
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self.cell_ac = factory.create(module_type="rom_base_cell", add_source_contact=self.route_layer, add_drain_contact=self.route_layer)
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self.poly_tap = factory.create(module_type="rom_poly_tap")
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def create_taps(self):
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self.tap_inst = {}
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for()
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#base cell with no contacts
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self.cell_nc = factory.create(module_name="base_mod_0_contact", module_type="rom_base_cell")
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#base cell with drain contact
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self.cell_dc = factory.create(module_name="base_mod_d_contact", module_type="rom_base_cell", add_drain_contact=self.route_layer)
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#base cell with source contact
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self.cell_sc = factory.create(module_name="base_mod_s_contact", module_type="rom_base_cell", add_source_contact=self.route_layer)
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#base cell with all contacts
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self.cell_ac = factory.create(module_name="base_mod_sd_contact", module_type="rom_base_cell", add_source_contact=self.route_layer, add_drain_contact=self.route_layer)
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self.poly_tap = factory.create(module_type="rom_poly_tap", strap_length=self.strap_spacing)
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self.gnd_rail = factory.create(module_type="rom_array_gnd_tap", length=self.row_size)
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def create_instances(self):
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self.tap_inst = {}
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self.cell_inst = {}
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self.cell_list = []
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self.current_row = 0
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#When rotated correctly rows are bit lines
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#list of current bitline interconnect nets, starts as the same as the bitline list and is updated when new insts of cells are added
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int_bl_list = self.bitline_names[0]
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#When rotated correctly rows are word lines
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for row in range(self.row_size):
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row_list = []
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#when rotated correctly cols are word lines
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#when rotated correctly cols are bit lines
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for col in range(self.column_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if(self.data[row][col] == 1):
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if row < self.row_size - 1 and row > 0 and self.data[row + 1][col] == 0 and self.data[row - 1][col] == 0:
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if self.data[row][col] == 1:
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# if dummy/0 cell above and below a 1, add a tx with contacts on both drain and source
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# if the first row and a 0 above, add both contacts
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# if the last row and 0 below add both contacts
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#(row == 0 and self.data[row + 1][col] == 0):
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if (row < self.row_size - 1 and row > 0 and self.data[row + 1][col] == 0 and self.data[row - 1][col] == 0) or \
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(row == self.row_size - 1 and self.data[row - 1][col] == 0):
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_ac)
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elif row > 0 and self.data[row - 1][col] == 0:
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# if dummy/0 is below and not above, add a source contact
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# if in the first row, add a source contact
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elif (row > 0 and self.data[row - 1][col] == 0):
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_sc)
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elif row < self.row_size - 1 and self.data[row + 1][col] == 0:
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elif (row < self.row_size - 1 and self.data[row + 1][col] == 0) or \
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(row == self.row_size - 1):
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_dc)
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else:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_nc)
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if row == self.row_size - 1 or self.get_next_cell_in_bl(row, col) == -1:
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print(self.cell_inst[row, col])
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bl_l = int_bl_list[col]
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bl_h = "gnd"
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else:
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bl_l = int_bl_list[col]
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int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
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bl_h = int_bl_list[col]
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self.connect_inst([bl_h, bl_l, self.wordline_names[0][row], "gnd"])
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self.connect_inst(["vdd", "gnd", "gnd"])
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else:
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy)
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self.connect_inst([])
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# when col = 0 bl_h is connected to vdd, otherwise connect to previous bl connection
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# when col = col_size - 1 connected to gnd otherwise create new bl connection
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#
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row_list.append(self.cell_inst[row, col])
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if col % self.strap_spacing == 0:
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name = "tap_r{0}_c{1}".format(row, col)
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self.tap_inst[row, col]=self.add_inst(name=name, mod=self.poly_tap)
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self.connect_inst([])
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name = "tap_r{0}_c{1}".format(row, self.column_size)
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#print(*row_list)
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self.tap_inst[row, self.column_size]=self.add_inst(name=name, mod=self.poly_tap)
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self.connect_inst([])
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self.cell_list.append(row_list)
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@ -130,19 +165,38 @@ class rom_base_array(bitcell_base_array):
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def place_tap(self, col):
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def place_taps(self):
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self.tap_pos = {}
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for row in range(self.row_size):
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for s_col in range(0, self.column_size, self.strap_spacing):
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col = s_col * self.strap_spacing
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tap_x = self.dummy.width * (col_offset)
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tap_x = self.dummy.width * col
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tap_y = self.dummy.height * row
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self.tap_pos[row, col] = vector(tap_x, tap_y)
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self.tap_inst[row, col].place(self.tap_pos[row, col])
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tap_x = self.dummy.width * self.column_size + self.poly_tap.width
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tap_y = self.dummy.height * row
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self.tap_pos[row, col] = vector(tap_x, tap_y)
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self.tap_inst[row, col].place(self.tap_pos[row, col])
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self.tap_pos[row, self.column_size] = vector(tap_x, tap_y)
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self.tap_inst[row, self.column_size].place(self.tap_pos[row, self.column_size])
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offset=vector(0, 0),
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def place_rails(self):
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#self.gnd_rail_inst = self.add_inst(name="gnd", mod=self.gnd_rail)
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#self.connect_inst([])
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print (self.mcon_width)
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rail_start = vector(-self.dummy.width / 2 , self.cell_inst[self.row_size - 1,0].uy() )
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rail_end = vector(self.dummy.height * (self.row_size ), self.cell_inst[self.row_size - 1,0].uy())
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self.add_layout_pin_rect_ends( name="gnd",
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layer="m1",
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start=rail_start,
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end=rail_end)
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def place_ptx(self):
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self.cell_pos = {}
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@ -42,20 +42,19 @@ class rom_base_cell(rom_dummy_cell):
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print(self.height)
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print(self.width)
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def add_pins(self):
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pin_list = ["bl_h", "bl_l", "wl"]
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dir_list = ["INOUT", "GROUND", "INPUT"]
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self.add_pin_list(pin_list, dir_list)
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def create_nmos(self):
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self.cell_inst = self.add_inst( name=self.name,
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self.cell_inst = self.add_inst( name=self.name + "_nmos",
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mod=self.nmos,
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)
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self.connect_inst(["bl_h", "wl", "bl_l", "gnd"])
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def add_pins(self):
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pin_list = ["bl_h", "bl_l", "wl", "gnd"]
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dir_list = ["INOUT", "INOUT", "INPUT", "GROUND"]
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self.add_pin_list(pin_list, dir_list)
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def place_nmos(self):
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@ -29,10 +29,9 @@ class rom_dummy_cell(design):
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#creates nmos for layout dimensions
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self.add_nmos()
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#set height and width such that the cell will tile perfectly by only ofsetting in the array by its width and height
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def create_layout(self):
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@ -47,6 +46,7 @@ class rom_dummy_cell(design):
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self.add_label("0,0", self.route_layer)
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# Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules
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@ -95,11 +95,11 @@ class rom_dummy_cell(design):
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def add_metal(self):
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wire_x = min(self.cell_diffusion_offset, 0) + min(self.poly_active_offset, 0)
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wire_x = min(self.cell_diffusion_offset, 0) + min(self.poly_active_offset, 0) - self.mcon_width * 0.5
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wire_y = 0.5 * (self.width - self.poly_extend_active_spacing)
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wire_start = vector( wire_x, wire_y )
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wire_end = vector(self.height, wire_y)
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wire_end = vector(self.height + self.mcon_width * 0.5, wire_y)
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# if self.route_layer == 'm1':
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@ -126,6 +126,7 @@ class rom_dummy_cell(design):
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# else:
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# add_drain = self.route_layer
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self.nmos = factory.create(module_type="ptx",
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module_name="nmos_rom_mod",
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tx_type="nmos",
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add_source_contact=self.add_source_contact,
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add_drain_contact=self.add_drain_contact
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@ -18,13 +18,12 @@ class rom_poly_tap(design):
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#for layout constants
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self.dummy = factory.create(module_type="rom_dummy_cell")
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pass
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def create_layout(self):
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self.place_via()
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self.add_boundary()
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if self.length < 0:
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if self.length != 0:
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self.place_strap(self.length)
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def add_boundary(self):
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@ -36,7 +35,7 @@ class rom_poly_tap(design):
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contact_width = self.poly_contact.width
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contact_x = contact_width * 0.5
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contact_x = - contact_width * 0.5 - self.dummy.width
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contact_y = self.dummy.poly.offset.x + (self.poly_width * 0.5)
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contact_offset = vector(contact_x, contact_y)
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